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High−level Instructions
F115
(FIFT)
P115
(PFIFT)
Outline
Defines the FIFO buffer conditions.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
"P115 (PFIFT)" is not available.
Program example
Trigger
R0
10
DF
n
D
Operands
Relay
Operand
Operand
WX WY WR WL
n
A
A
D
N/A
A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
(*2) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*3) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
When the execution condition (trigger) R0 is on, the area headed by DT0 is defined in the FIFO buffer area.
The size of the FIFO buffer (K256) is stored in DT0, the number of data items stored is stored in DT1 (with a
default value of K0), and the FIFO pointer (with a default value of H0000) is stored in DT2.
When n = K256, the 256 words from DT3 to DT258 are defined as the data storage area.
15
0
DT0
K256
Memory size of FIFO buffer (n)
DT1
K0
Number of stored data items (words)
DT2
0
0
FIFO pointer
DT3
DT257
DT258
3 − 254
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FIFO buffer definition
Ladder Diagram
Ladder Diagram
F115 FIFT, K 256, DT 0
16-bit equivalent constant or 16−bit area for specifying the memory size of
FIFO buffer
Starting 16-bit area of FIFO buffer
Timer/Counter
SV
EV
DT
A
A
A
A
A
A
A
A
Data storage area
(256 words)
n
D
Index
Register
register
LD
IX
IY
FL
(*1)
(*2)
(*3)
A
A
A
A
A
A
A
A
N/A
N/A
Transmission is enabled by the F0 (MV)
instruction (overwriting is possible).
Boolean
Address
Instruction
10
ST
R
11
DF
12
F115
(FIFT)
K
256
DT
Constant
Index
Index
modifier
K
H
A
A
A
N/A
N/A
A
A:
Available
N/A: Not Available
0
0
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