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F36
(D+1)
P36
(PD+1)
Outline
Adds 1 to 32-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
"P36 (PD+1)" is not available.
Program example
Trigger
R0
10
D
Operands
Relay
Operand
Operand
WX WY WR
D
N/A
A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Adds 1 to the content of data registers DT1 and DT0 when trigger R0 turns on.
Higher 16 bits
Lower 16 bits
Contents of
Contents of
DT1
DT0
+1
Store to DT1
Store to DT0
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32-bit data increment
[(D + 1, D) + 1 → (D + 1, D)]
Ladder Diagram
Ladder Diagram
F36 D+1 , DT 0
D
Lower 16-bit area of 32-bit data to be increased by 1
Timer/Counter
WL
SV
EV
DT
(*1)
A
A
A
A
The specified data area and the
following data area are handled
together as 32−bit data.
Index
Register
register
LD
FL
IX
IY
(*1)
(*2)
(*3)
(*4)
A
A
A
A
N/A
High−level Instructions
Boolean
Address
Instruction
10
ST
R
11
F 36
(D+1)
DT
Constant
Index
Index
modifier
K
H
N/A
N/A
A
A:
Available
N/A: Not Available
3 − 87
0
0
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