Panasonic FP-E Programming Manual page 500

Fp series
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High−level Instructions
F103
(DSHL)
P103
(PDSHL)
Outline
Shifts a specified number of bits to the left in bit units.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
"P103 (PDSHL)" is not available.
Program example
Trigger
R0
10
F103 DSHL, DT10,
D
n
Operands
Relay
Operand
Operand
WX WY WR WL
D
N/A
A
n
A
A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
Description
Shifts n bits of the 32-bit area specified by D to the left (to the higher bit position) when the trigger turns on.
[n bits]
15
CY
The data in the nth
bit is transferred to
R9009 (carry flag).
When the n bits are shifted to the left,
− The n bits starting from bit position 0 are filled with 0s.
− The data in the nth bit is transferred to special internal relay R9009 (carry flag).
3 − 236
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Left shift of n bits in a 32-bit data
Ladder Diagram
Ladder Diagram
D
Lower 16-bit area of 32-bit data to be shifted to the left
16-bit equivalent constant or 16-bit area (specifies number of shifted bits)
Range of n: K0 to K255 (H0 to HFF)
Timer/Counter
SV
EV
A
A
A
A
A
A
A
A
[D+1]
[D]
0 15
[n bits] starting from bit position 0
are filled with 0s.
DT 2
n
Index
Register
register
FL
DT
LD
I
(*1)
A
A
A
A
A
A
A
A
0
00000000
Boolean
Address
Instruction
10
ST
R
11
F103
DT
DT
Constant
Index
Index
modifier
K
H
f
N/A N/A N/A
A
A
A
N/A
A
A:
Available
N/A: Not Available
0
(DSHL)
10
2
Integer
Integer
device
N/A
N/A

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