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F61
(DCMP)
P61
(PDCMP)
Outline
The two specified 32−bit data are compared and the result is output to
the special internal relay.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
"P61 (PDCMP)" is not available.
Program example
Trigger
R0
50
F61 DCMP , DT 0 , DT 10
R0
R900A
60
R0
R900B
63
R0
R900C
66
S1
S2
Operands
Relay
Operand
Operand
WX WY WR
S1
A
A
S2
A
A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ, FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
Phone: 800.894.0412 - Fax: 888.723.4773 - Web: www.clrwtr.com - Email: info@clrwtr.com
32-bit data comparison
Ladder Diagram
Ladder Diagram
S1
32-bit equivalent constant or lower 16-bit area of 32-bit data to be compared
32-bit equivalent constant or lower 16-bit area of 32-bit data to be compared
Timer/Counter
WL
SV
EV
DT
(*1)
A
A
A
A
A
A
A
A
S2
Y10
Y11
Y12
Index
Register
register
LD
FL
IX
IY
(*1)
(*2)
(*3)
A
A
A
A
N/A
A
A
A
A
N/A
High−level Instructions
Boolean
Address
Instruction
50
ST
R
51
F 61
(DCMP)
DT
DT
60
ST
R
61
AN
R 900A
62
OT
Y
63
ST
R
64
AN
R 900B
65
OT
Y
66
ST
R
67
AN
R 900C
68
OT
Y
Constant
Index
Index
modifier
K
H
A
A
A
A
A
A
A:
Available
N/A: Not Available
3 − 131
0
0
10
0
10
0
11
0
12
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