Sru Time Slot Integration - Zhone IMACS 8000 User Manual

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LD-SRU Card User Screens and Settings
SR TS
The Subrate Time Slot (SR TS) indicates the subrate position within the DS0 time slot the port
will occupy (see Figure 16-4). If a framing is selected, only one subrate time slot is supported
and the SR TS setting will default to 1. If b-5 framing is selected, the available subrate time
slots are 1 to 5. If adpcm or hlink are chosen for the frame parameter, this field will show n/a.
In b-5 framing, if circuits with speeds greater than 9.6 kbps are assigned to the subrate time
slot, adjacent subrate time slots must be available to accommodate their size. A 19.2 kbps
circuit would occupy two contiguous subrate time slots (leaving space for up to three 9.6 kbps
circuits) and a 38.4 kbps circuit would occupy four contiguous subrate time slots (leaving
space for one 9.6 kbps circuit).
The SR TS number selected will be the first segment occupied by this circuit. If a 28.8 kbps
circuit occupies three segments of the b-5 frame, selecting SR TS 1 will assign it to segments
1, 2 and 3. Segments 4 and 5 may be assigned either independently to 9.6 (or less) kbps circuits
in SR TS 4 and 5 or combined for a 19.2 kbps circuit assigned to SR TS 4.
If a circuit exceeds the slots necessary to accommodate it, such as a 38.4 kbps circuit to SR
TS 3 in b-5 framing, the message "Invalid SR TS" will be displayed. If a circuit requires more
space than the SR TS has available, such as having a 38.4 kbps circuit in SR TS 1 and then
attempting to assign a 19.2 kbps circuit to SR TS 4, the message "SR TS overlapping" will be
displayed.
16-8
increments (i.e. a 19.2Kbps circuit would take SRU timeslots #1 and #2)
Figure 16-4.SRU Time Slot Integration
Model No.
LDSRU-10P Card
Data Cards