Figure 8.5C Interval Timer Function (One-Shot Timer Mode) Settings; Figure 8.5D Operation In One-Shot Timer Mode - Fujitsu F2MC-8L MB89620 Series Hardware Manual

l One-shot timer mode
Figure 8.5c shows the settings required to operate in one-shot timer mode.

Figure 8.5c Interval Timer Function (One-shot Timer Mode) Settings

On activation, the RLBR register value is loaded to the counter and the counter starts counting-
down on the rising edge of the selected count clock. When the counter value underflows (01
00 ), the counter inverts the timer output bit (PCR2: TO) value, automatically clears the counter
H
operation enable bit (PCR1: EN = "0") to stop counter operation, and sets the underflow (01
00 ) interrupt request flag bit (PCR1: UF = "1") on the next rising edge of the count clock.
H
Figure 8.5d shows the operation in one-shot timer mode.
Counter value
*: If the PWC reload buffer register (RLBR) value is modified during operation, the new value is used from the next cycle.
Check: Do not modify PCR2 when the counter is operating (PCR1: EN = "1").
Notes: • The UF bit is set to "1" if a counter value underflows (01
interrupt request enable bit (PCR1: IE).
• When the counter is stopped (PCR1: EN = "0") while the interval timer function is selected, the TO
bit maintains the value it had immediately before the counter stopped.
MB89620 series
Bit 7 Bit 6
PCR1 EN TOE
1 1
PCR2 FC RM
0 1
RLBR Sets interval time (counter initial value).
FF
H
80
H
00
H
Timer cycle
RLBR value
(FF )
H
UF bit
EN bit
Automatic clear
Invert
TOE bit
WTO pin
(TO bit)
For an initial value of "1" on activation

Figure 8.5d Operation in One-shot Timer Mode

Bit 5 Bit 4 Bit 3 Bit 2
IE — — UF
TO — C1 C0
RLBR value modified (FF
Cleared by the program
Reactivate Automatic clear
Reactivates with the initial value unchanged ("0")
→ 00
H
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC)
Bit 1 Bit 0
IR BF
× ×
W1 W2
: Used bit
× : Unused bit
× ×
1 : Set "1".
0 : Set "0".
Time
→ 80
*
)
H H
Reactivate Automatic clear
), regardless of the value of the
H
→
H
→
H
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