Download Print this page

Address Generation - ARM ETB11 Technical Reference Manual

Advertisement

Functional Description
2.6

Address generation

2.6.1
Write address generation
2.6.2
Read address generation
2-10
There are two RAM address pointer registers:
the RAM Write Pointer Register is selected during trace capture
the RAM Read Pointer Register is used as the RAM address source:
when trace capture is disabled
if software access to registers is disabled.
TraceCaptEn selects which pointer is used.
The RAM Write Pointer Register sets the trace RAM start address. It must be
programmed before trace capture is enabled. The RAM Write Pointer Register
increments when the DataValid flag is asserted by the Data Formatter. Reading the
register returns the current RAM Write Pointer Register value. The RAM Write Pointer
Register can be read back at any time. However if the TAP controller clock, DBGTCK,
is asynchronous to CLK, the value might be indeterminate if read while trace capture
is enabled. Therefore, the pointer must be accessed when TraceCaptEn is deasserted.
The RAM Write Pointer Register is not affected by AHB writes to the RAM.
When trace capture and software access to registers are disabled, the RAM Read Pointer
Register generates the RAM address. Updating the RAM Read Pointer Register
automatically triggers a RAM access to ensure the RAM data output is up-to-date.
Either writing to the RAM Read Pointer Register or reading the RAM Data Register
updates the RAM Read Pointer Register. The RAM Read Pointer Register increments
each time the RAM Data Register is read. The RAM Read Pointer Register can be
accessed at any time. Reading the RAM Read Pointer Register returns its current value,
the RAM read address. The RAM Read Pointer Register is not affected by AHB reads
from the RAM.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
ARM DDI 0275D

Advertisement

loading