Debug Signals; A.5 Debug Signals - ARM ARM9TDMI Technical Reference Manual

ARM9TDMI Signal Descriptions
A.5

Debug signals

Name Direction
COMMRX Output
COMMTX Output
DBGACK Output
DBGEN Input
DBGRQI Output
DEWPT Input
EDBGRQ Input
EXTERN0 Input
EXTERN1 Input
IEBKPT Input
INSTREXEC Output
A-8
Description
Communications Channel Receive. When HIGH, this signal denotes that the comms
channel receive buffer contains data waiting to be read by the ARM9TDMI.
Communications Channel Transmit. When HIGH, this signal denotes that the comms
channel transmit buffer is empty and the ARM9TDMI can write new data to the comms
channel.
Debug Acknowledge. When HIGH, this signal indicates the ARM9TDMI is in debug
state.
Debug Enable. This input signal allows the debug features of the ARM9TDMI to be
disabled. This signal should be LOW only when debugging will not be required.
Internal Debug Request. This signal represents the debug request signal which is
presented to the processor core. This is a combination of EDBGRQ, as presented to the
ARM9TDMI, and bit 1 of the debug control register.
Data Watchpoint. This is an input which allows external hardware to halt execution of
the processor for debug purposes. If HIGH at the end of phase 1 following a data memory
request cycle, it will cause the ARM9TDMI to enter debug state.
External Debug Request. When driven HIGH, this causes the processor to enter debug
state after execution of the current instruction completes.
External Input 0. This is an input to watchpoint unit 0 of the EmbeddedICE macrocell in
the processor which allows breakpoints/watchpoints to be dependent on an external
condition.
External Input 1. This is an input to watchpoint unit 1 of the EmbeddedICE macrocell in
the processor which allows breakpoints/watchpoints to be dependent on an external
condition.
Instruction Breakpoint. This is an input which allows a external hardware to halt the
execution of the processor for debug purposes. If HIGH at the end of phase 1 following
an instruction memory request cycle, it causes the ARM9TDMI to enter debug state if
the relevant instruction reaches the execute stage of the processor pipeline.
Instruction Executed. Indicates that in the previous cycle the instruction in the execute
stage of the pipeline passed its condition codes, and was executed.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Table A-5 Debug signals
ARM DDI0145B