S1D13506 Hardware Configuration; Register/Memory Mapping - Epson S1D13506 Technical Manual

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4.3 S1D13506 Hardware Configuration

S1D13506
Pin Name
MD[3:1] 110 = PowerPC host bus interface selected
MD4 Little Endian
MD5 Wait# signal is active high
MD9 Reserved
MD11 Alternate Host Bus Interface Selected
MD12 BUSCLK input divided by two
MD15
WAIT# is always driven
= required settings for MPC821 support.

4.4 Register/Memory Mapping

S1D13506
X25B-G-008-03
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The following table shows those configuration settings important to the MPC821 host bus
interface.
Table 4-2: Summary of Power-On/Reset Options
value on this pin at rising edge of RESET# is used to configure: (1/0)
1
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
S1D13506 is addressed starting at 40 0000h. A total of 4M bytes of address space is used,
where the lower 2M bytes is reserved for the S1D13506 on-chip registers and the upper 2M
bytes is used to access the S1D13506 display buffer.
Epson Research and Development
0
Big Endian
Wait# signal is active low
Configure SUSPEND# pin as Hardware Suspend
Enable
Primary Host Bus Interface Selected
BUSCLK input not divided
WAIT# is floating if S1D13506 is not selected
Interfacing to the Motorola MPC821 Microprocessor
Vancouver Design Center
Issue Date: 01/02/08