Internal Clocks; Table 7-13: Internal Clock Requirements - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center

7.2.2 Internal Clocks

Symbol
f
MCLK
f
LCD PCLK
f
CRT/TV PCLK
f
MediaPlug Clock
1. The maximum CRT pixel clock is 40MHz.
The TV pixel clock for NTSC output is fixed at 14.318MHz.
The TV pixel clock for PAL output is fixed at 17.734MHz.
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-13: Internal Clock Requirements

Parameter
Memory Clock Frequency
LCD Pixel Clock Frequency
CRT/TV Pixel Clock Frequency
MediaPlug Clock Frequency
Min Max Units
0 40 MHz
0 40 MHz
0 Note 1 MHz
0 10 MHz
S1D13506
X25B-A-001-12
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