Host Bus Interface Signal Descriptions - Epson S1D13506 Technical Manual

Page 12

3.2 Host Bus Interface Signal Descriptions

S1D13506
X25B-G-013-03
The S1D13506 PC Card Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
driven by one of the SA-1110 signals SDCLK1 or SDCLK2 (the example implementa-
tion in this document uses SDCLK2). For further information, see Section 4.3, "Perfor-
mance" on page 14.
• The address inputs AB[20:1], and the data bus DB[15:0], connect directly to the
SA-1110 address (A[20:1]) and data bus (D[15:0]), respectively. MD4 must be set to
select little endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low by nCSx (where x is the SA-1110 chip select
used) whenever the S1D13506 is accessed by the SA-1110.
• WE1# and RD/WR# connect to nCAS1 and nCAS0 (the byte enables for the high-order
and low-order bytes). They are driven low when the SA-1110 is accessing the
S1D13506.
• RD# connects to nOE (the read enable signal from the SA-1110).
• WE0# connects to nWE (the write enable signal from the SA-1110).
• WAIT# is a signal output from the S1D13506 that indicates the SA-1110 must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since SA-1110
accesses to the S1D13506 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13506 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. For the SA-1110, this signal should be set active low
using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for this Host Bus Interface and should be tied
high (connected to V
DD
• The RESET# (active low) input of the S1D13506 may be connected to the system
RESET.
).
Interfacing to the StrongARM SA-1110 Processor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/08