Single Monochrome 8-Bit Panel Timing; Figure 7-24: Single Monochrome 8-Bit Panel Timing - Epson S1D13506 Technical Manual

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7.5.2 Single Monochrome 8-Bit Panel Timing

FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13506
X25B-A-001-12
LINE1 LINE2 LINE3
1-1 1-9
1-2 1-10
1-3 1-11
1-4 1-12
1-5 1-13
1-6 1-14
1-7 1-15
1-8 1-16

Figure 7-24: Single Monochrome 8-Bit Panel Timing

= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
VDP
LINE4 LINE479 LINE480
HDP
Epson Research and Development
Vancouver Design Center
VNDP
LINE1 LINE2
HNDP
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
Hardware Functional Specification
Issue Date: 02/03/26