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7.3.22 CONFIG1 (CONFIG1) R/W ..................19 7.3.23 Test (TEST) R(/W) ....................20 7.3.24 Revision Reg. (REVISION) R ..................20 7.4 SCSI Control Commands ......................20 7.4.1 Control Commands and Command Codes ..............20 7.4.2 Description of Each Control Command................21 7.4.3 Command Execution and State Transition ..............28 Rev.1.1 EPSON...
8. ELECTRICAL CHARACTERISTICS....................30 8.1 Absolute Maximum Ratings......................30 8.2 Recommended operational conditions..................30 8.3 DC Characteristics........................30 8.4 AC Characteristics........................33 8.4.1 CPU Interface.......................34 8.4.2 SCSI Interface ......................36 8.4.3 Port Interface ........................49 8.4.4 Others...........................53 9. EXAMPLES OF CONNECTION.......................56 10. EXTERNAL DIMENSIONS DRAWING ..................57 EPSON Rev.1.1...
S1R72104 Technical Manual 1. DESCRIPTION S1R72104 is a SCSI interface control IC compatible with SCAM and FAST20 transfer. 2. FEATURES «CPU Interface» Connectable to a general-purpose CPU «SCSI Interface» Compatible with SCSI-2 (10Mbps (synchronous), 5Mbps (asynchronous)) Compatible with SCSI-3 FAST20 (20Mbps (synchronous)) Compatible with SCAM Lv.1 (compatible with Lv.2 with firmware)
S1R72104 Technical Manual 5. PIN DESCRIPTION The control signal with “X” at the head of a pin name is LOW-active. Pin No. Symbol Functional description Remarks SCSI interface-related matters (18) XSDB0 Is/Otr SCSI data signal (SD0 to SD7) Drive capability 48mA...
S1R72104 Technical Manual Pin No. Symbol Functional description Remarks CPU interface-related matters (17) Address input pin (AD0 to AD4) Ipu/O Data pin (DB0 to DB7) Drive capability 3mA Ispu Chip select signal for accessing internal register XINT Interrupt request output signal...
S1R72104 Technical Manual 6. FUNCTIONAL DESCRIPTION 6.1 CPU Interface Circuit This block can be interfaced to a general-purpose CPU. It controls the interface with the CPU generally. If XCS signal from CPU is LOW, the block can access the internal register. It decodes the address bus AD4 to AD0 to generate the address of the internal register.
S1R72104 Technical Manual 6.6 PLL Circuit (Internal System Clock Generating Section) This IC has the function to generate 40MHz required for the internal circuit from the clock generated by the oscillation circuit or inputted from EXCK pin by using PLL circuit.
S1R72104 Technical Manual 7. FUNCTION OF REGISTERS 7.1 List of Registers Address Register name Abridged name Main Interrupt Status MAININT SCSI Interrupt Status 1 SCSIINT1 SCSI Interrupt Status 2 SCSIINT2 - Reserved - - Reserved - - Reserved - - Reserved -...
S1R72104 Technical Manual 7.3 Detailed Description of Each Register 7.3.1 Main Interrupt Status (MAININT) R/W When the IC interrupted CPU, the CPU first reads this register for processing the interruption to get to know which interrupt status register is the factor.
S1R72104 Technical Manual 7.3.2 SCSI Interrupt Status 1 (SCSIINT1) R/W Shows the result of a SCSI control command executed. The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It clears the bit by writing again the value read.
S1R72104 Technical Manual 7.3.3 SCSI Interrupt Status 2 (SCSIINT2) R/W Shows the result of a SCSI control command executed. The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It clears the bit by writing again the value read.
S1R72104 Technical Manual 7.3.6 SCSI Mode Select1 (SCSIMODE1) R/W Makes the operational settings related to SCSI interface. STPPE ATNPE STATN AUTO RINH SINH DIRECT SPCEN SCSI PARITY CHECK ENABLE SCSI DIRECT ACCESS ENABLE SELECTION INHIBIT RESELECTION INHIBIT AUTO SEND STATUS/MESSAGE...
S1R72104 Technical Manual 7.3.8 SCSI Data (SCSIDATA) R/W The CPU accesses this register when it controls SCSI data bus directly. For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah). The status of each signal is stored as “active HIGH”. DIRECT setting does not decide whether parity bit is output or not;...
S1R72104 Technical Manual 7.3.10 SCSI Own ID (OWNID) R/W Sets the SCSI-ID of this IC itself. OID2 OID2 OID0 7.3.11 Source/Destination ID (SDID) R/W Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made.
S1R72104 Technical Manual 7.3.14 FIFO Data (FIFODATA) R/W This is a register to access SCSI-FIFO from CPU. 7.3.15 Non DMA Transfer Size (NDMASIZ) R/W Sets the bytes number of data transferred in Non-DMA mode (the message and command phases). In Read mode, the register allows to read out the size of data yet to be transferred.
S1R72104 Technical Manual 7.3.20 DMA Transfer Byte Count 0 (DTBC0) R/W Sets the least significant byte of the byte-length (3 bytes) for DMA transfer. DBC7 DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0 7.3.21 CONFIG0 (CONFIG0) R/W Sets the operation mode of the IC.
S1R72104 Technical Manual * Operational settings of the port interface Shown below is a list of the operational settings made by the bit setting. 1) Switching master/slave of the port by PSLV bit PDREQ XPDACK XPRD/XPWR Remarks PSLV=0 Input Output...
S1R72104 Technical Manual 7.3.23 Test (TEST) R(/W) Used for testing a LSI. Basically, writing in this register is prohibited. CKOUTbit is valid, however, even when no test is done. If this bit is used, be sure to set all the other bits to “0”.
S1R72104 Technical Manual 7.4.2 Description of Each Control Command Abort_SCSI(01H) Suspends a SCSI control command under execution. After suspension, this command sets SABT bit of MAININT register and the status block, causing interruption. This command, if issued in a non-operational condition, is ignored.
S1R72104 Technical Manual Select_WithATN_Command(0AH) Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase. This command is valid in either disconnected or connected condition. It causes a command error if issued when any other command is under execution.
S1R72104 Technical Manual After the execution, the IC enters Initiator mode. Reselect(0DH) Executes the re-selection phase.. Valid only when it is not connected. If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other command is under execution then, it continues execution.
S1R72104 Technical Manual It causes interruption. CPU reads a command from FIFO In Initiator mode CPU issues this command after setting the command byte number in NON-DMA data-size register. Then it writes the command data in FIFO. The IC acts as follows: Negates XSACK if it is asserted at the start of execution.
S1R72104 Technical Manual Non-DMA_Data_Out(14H) Executes the data-out phase between SCSI and CPU interface. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
S1R72104 Technical Manual Non-DMA_Data_In(16H) Executes the data-in phase between SCSI and CPU interface. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
S1R72104 Technical Manual Message_In (18H) Executes the message-in phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If it is issued in the disconnected condition, It sets SCSIINT2 and CMDER bits, causing interruption.
S1R72104 Technical Manual Status_Message(1AH) Executes the message-in phase after executing the status phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
S1R72104 Technical Manual 7.5 Others and Cautions about Operation Operation responding to the selection without SCSI-1 arbitration phase The IC operates responding to the selection of only a target ID of SCSI-1 as mentioned below. Note that there occurs no (automatic) transition to the message or command phase after selection, as in the usual cases after Wait_selection command.
S1R72104 Technical Manual 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings = 0[V] Item Symbol Ratings Unit Supply voltage -0.3 to +6.0 -0.3 to +4.6 Input voltage -0.3 to HV + 0.5 -0.3 to LV + 0.5 Output voltage -0.3 to HV + 0.5...
S1R72104 Technical Manual (2) TTL input characteristics (Ta = 0 to70°C, V =0V) Names of signals covered: AD0 to 4,DB0 to 7, PD0 to 15, EXCLK, XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO Item Symbol Conditions Min. Typ. Max. Unit HIGH level =5.5V...
S1R72104 Technical Manual (7) Output characteristics (Ta = 0 to 70°C, V = 0V) (I = 3mA) Names of signals covered: XPDACK, PD0 to 15, DB0 to 7, XPRD, XPWR Item Symbol Conditions Min. Typ. Max. Unit HIGH level =5.0V Output voltage =-1.5mA...
S1R72104 Technical Manual 8.4 AC Characteristics Measurement conditions of AC characteristics: Ta = 0 to 70 HV = 5V±10% LV = 3.3V±0.3V = 0V DC level to decide input 0.8V to 2.4V Operating clock = 40MHz oscin Loading conditions of output pins except SCSI pins Drives load capacitance of 50pF and 1TTL.
S1R72104 Technical Manual 8.4.3 Port Interface 126.96.36.199 DMA Read (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72104 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPRD(I) PD15-0(0) XPWR(I) Symbol Specification Min. Typ. Max. Unit XPWR → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPWR XPDACK hold time XPRD ↓...
S1R72104 Technical Manual 188.8.131.52 DMA Write (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72104 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPWR(I) PD15-0(I) XPRD(I) Symbol Specification Min. Typ. Max. Unit XPRD → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPRD XPDACK hold time XPWR ↓...
S1R72104 Technical Manual 184.108.40.206 DMA Write (PSLV=0: Master mode) Prosessor S1R72104 HOST Direction of data transfer PDREQ(I) XPDACK(0) XPWR(0) PD15-0(0) Symbol Specification Min. Typ. Max. Unit XPWR ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPWR ↓...
S1R72104 Technical Manual 220.127.116.11 DMA Read (PSLV=0: Master mode) Prosessor Direction of data transfer S1R72104 HOST PDREQ(I) XPDACK(0) XPRD(0) PD15-0(I) Symbol Specification Min. Typ. Max. Unit XPRD ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPRD ↓...
S1R72104 Technical Manual 8.4.4 Others 18.104.22.168 OSCIN Input Clock (ex.40MHz) Note: Maximum input voltage: LV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 (1/f) CLK HIGH width *1 (1/f)×0.4 (1/f)×0.6 CLK LOW width *1 (1/f)×0.4 (1/f)×0.6 CLK rise time...
S1R72104 Technical Manual 22.214.171.124 EXCLK Input Clock (ex.40MHz) Note: Maximum input voltage: HV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 (1/f) CLK HIGH width *1 (1/f)×0.4 (1/f)×0.6 CLK LOW width *1 (1/f)×0.4 (1/f)×0.6 CLK rise time...
S1R72104 Technical Manual 126.96.36.199 XRESET Input Pulse Width XRESET Symbol Specification Min. Typ. Max. Unit XRESET LOW width 188.8.131.52 TESTMON (CLKOUT = HIGH) Output Pulse * When PLL is operated (When PLL is not used, the waveform inputted is output to CLKINorEXCLK pin.)
S1R72104 Technical Manual 10. EXTERNAL DIMENSIONS DRAWING Plastic QFP15-100 pin ±0.4 ±0.1 INDEX +0.1 0.18 -0.05 +0.05 0.125 -0.025 0° 10° ±0.2 Unit : mm Rev.1.1 EPSON...
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