Epson S1D13506 Technical Manual page 408

Page 18
S1D13506
X25B-B-001-02
Non-display period
Frame Rate
Pixel Clock
TFT/FPLINE (pixels)
eight pixels. If a manually entered panel width is not a
multiple of eight pixels a notification box appears and
13506CFG rounds up the value to the next allowable
width.
It is recommended that these automatically generated
non-display values be used without adjustment.
However, manual adjustment may be useful in fine
tuning the non-display width and the non-display
height.
As a general rule passive LCD panels and some CRTs
are tolerant of a wide range of non-display times. Active
panels, TVs and some CRTs are far less tolerant of
changes to the non-display period.
Select the desired frame rate (in Hz) from the drop-
down list. The values in the list are the range of possible
frame rates using the currently selected pixel clock. To
change the range of frame rates, select a different Pixel
Clock rate (in MHz).
Panel dimensions are fixed therefore frame rate can
only be adjusted by changing either PCLK or non-
display period values. Higher frame rates correspond to
smaller horizontal and vertical non-display values, or
higher frequencies.
Select the desired Pixel Clock (in MHz) from the drop-
down list. The range of frequencies displayed is
dependent on settings selected on the Clocks tab.
For example:
If CLKI is chosen to be Auto and LCD PCLK is sourced
from CLKI on the Clocks tab, then the range for Pixel
Clock will range from 1.5 MHz to 80 MHz.
Selecting a fixed LCD PCLK on the Clocks tab, say
25.175 MHz, will result in only four selections: 6.293,
8.392, 12.587, and 25.175 MHz. (these frequencies
represent the four possible frequencies from a fixed
25.175 MHz input clock divided by the PCLK divider).
These settings allow fine tuning of the TFT/D-TFT line
pulse parameters and are only available when the
selected panel type is TFT. Refer to S1D13506
Hardware Functional Specification, document number
X25B-A-001-xx for a complete description of the
FPLINE pulse settings.
Epson Research and Development
Vancouver Design Center
13506CFG Configuration Program
Issue Date: 01/03/14