Table 7-1: Generic Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Clock frequency
CLK
T Clock period
CLK
t2 Clock pulse width high
t3 Clock pulse width low
A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,
t4
RD1#= 0 or WE0#, WE1#= 0
A[20:1], M/R# hold from rising edge of either RD0#, RD1# or WE0#,
t5
WE1#
t6 CS# hold from rising edge of either RD0#, RD1# or WE0#, WE1#
t7 Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low
t8 Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# tri-state
D[15:0] setup to third CLK where CS# = 0 and WE0#, WE1# = 0 (write
t9
cycle)
t10 D[15:0] hold (write cycle)
t11 Falling edge RD0#, RD1# to D[15:0] driven (read cycle)
t12 D[15:0] setup to rising edge WAIT# (read cycle)
t13 Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-1: Generic Timing

Parameter
3.0V 5.0V
Min Max Min Max
50 50
1/f 1/f
CLK CLK
6 6
6 6
4 3
0 0
0 0
4 21 3 13
3 14 2
0 0
0 0
3 3
0 0
7 31 4 15
X25B-A-001-12
Page 49
Units
MHz
ns
ns
ns
ns
ns
ns
ns
7 ns
ns
ns
ns
ns
ns
S1D13506