Dual Color 16-Bit Panel Timing With External Circuit; Figure 7-43: 16-Bit Dual Color Panel Timing With External Circuit - Epson S1D13506 Technical Manual

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7.5.11 Dual Color 16-Bit Panel Timing with External Circuit

FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel

Figure 7-43: 16-Bit Dual Color Panel Timing with External Circuit

VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 02/03/26
VDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
1 -R 1
1-G 2 1 -B 3
1-G1 1-B2 1-R4
1 -B 1 1 -R 3 1 -G 4
1-G3 1 -B 4
1 -R 2
241-R1 241-G2 241-B3
241-G1 241-B2 241-R4
2 41 -B 1 2 4 1 -R 3 2 41 -B 4
2 4 1 -R 2 2 4 1-G 3 2 41 -B 4
1 -R 1
1-G1
1-B1
1-R2
1-G2
1 -B 2
1-R3
1-G 3
241-R1
241-G1
241-B1
241-R2
2 4 1-G 2
2 41 -B 2
241-R3
2 4 1-G 3
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
VNDP
LINE 239/479 LINE 240/480
HDP
1 -G 6 3 8 1 -B 6 3 9
1 - B 6 3 8 1 - R 6 4 0
1-G640
1 -R6 3 9
1 -G 6 3 9 1 -B 6 4 0
241- 241-
G638 B639
241- 241-
B638 R640
241- 241-
R639 G 640
241- 241-
G 639 B640
1-G638
1-B638
1-R639
1-G639
1 -B 6 3 9
1 - R 6 4 0
1 -G 6 4 0
1 -B 6 4 0
2 4 1 -G 6 3 8
2 4 1 -B 6 3 8
2 4 1 -R 6 3 9
2 4 1 -G 6 3 9
241-
B639
241-
R 640
241-
G 640
241-
B640
Page 111
LINE 1/241 LINE 2/242
HNDP
S1D13506
X25B-A-001-12