Epson S1D13505F00A Manuals

Epson S1D13505F00A Manuals

Manuals and User Guides for Epson S1D13505F00A. We have 1 Epson S1D13505F00A manual available for free PDF download: Technical Manual

Epson S1D13505F00A Technical Manual

Epson S1D13505F00A Technical Manual (320 pages)

Embedded RAMDAC LCD/CRT Controller

Brand: Epson | Category: Controller | Size: 9.85 MB

Table of Contents

Section 1

6
Section 2

140
- Introduction
  143
- Initialization
  144
- Miscellaneous
  146
- Display Buffer Location
  147
- Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
  147
- Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
  147
- Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)
  148
- Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
  148
- Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades)
  149
- Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)
  149
- Look -U P Table (Lut)
  150
- Look-Up Table Registers
  150
- Look-Up Table Organization
  151
- Advanced Techniques
  157
- Virtual Display
  157
- Examples
  158
- Registers
  158
- Panning and Scrolling
  159
- Registers
  160
- Examples
  161
- Registers
  162
- Split Screen
  162
- Examples
  163
- Introduction to LCD Power Sequencing
  164
- Lcd Power Sequencing and Power Save Modes
  164
- Registers
  164
- LCD Enable/Disable
  165
- Hardware Cursor
  166
- Introduction
  166
- Registers
  166
- Examples
  168
- Limitations
  168
- No Top/Left Clipping on Hardware Cursor
  168
- Reg[29H] and Reg[2Bh]
  168
- Reg[30H]
  168
- Hardware Rotation
  169
- Introduction to Hardware Rotation
  169
- S1D13505 Hardware Rotation
  169
- Registers
  170
- Examples
  171
- Limitations
  171
- Crt Considerations
  173
- CRT Only
  173
- Introduction
  173
- Simultaneous Display
  173
- Identifying the S1D13505
  174
- API for 13505HAL
  175
- Hardware Abstraction Layer (Hal)
  175
- Initialization
  175
- Introduction
  175
- General HAL Support
  178
- Advanced HAL Functions
  181
- Register / Memory Access
  183
- Color Manipulation
  185
- Drawing
  187
- Hardware Cursor
  189
- Ink Layer
  192
- Power Save
  195
- X-LIB Support
  196
- Introduction
  197
- Sample Code
  197
- Sample Code Using the 13505HAL API
  197
- Sample Code Without Using the 13505HAL API
  199
- Header Files
  205
- Appendix Supported Panel Values
  212
Section 3

216
- 13505Cfg Configuration Program
  219
- Installation
  219
- S1D13505 Supported Evaluation Platforms
  219
- Usage
  219
- 13505CFG Configuration
  220
- General Page
  221
- Memory Page
  222
- Panel Page
  223
- CRT Page
  224
- Default Page
  225
- Open Dialog Box
  226
- Save as Dialog Box
  227
- Example
  228
- Comments
  229
- Sample Program Messages
  230
- 13505Show
  231
- 13505Show Demonstration Program
  231
- Installation
  231
- S1D13505 Supported Evaluation Platforms
  231
- 13505SHOW Examples
  232
- Usage
  232
- Comments
  233
- Program Messages
  234
- 13505Splt
  235
- 13505Splt Display Utility
  235
- Installation
  235
- S1D13505 Supported Evaluation Platforms
  235
- 13505SPLT Example
  236
- Comments
  236
- Usage
  236
- Program Messages
  237
- 13505Virt
  238
- 13505Virt Display Utility
  238
- Installation
  238
- S1D13505 Supported Evaluation Platforms
  238
- 13505VIRT Example
  239
- Comments
  239
- Usage
  239
- Program Messages
  240
- 13505Play
  241
- 13505Play Diagnostic Utility
  241
- Installation
  241
- S1D13505 Supported Evaluation Platforms
  241
- Usage
  242
- 13505PLAY Example
  243
- Comments
  244
- Scripting
  244
- Program Messages
  245
- 13505Bmp
  246
- 13505Bmp Demonstration Program
  246
- 13505BMP Examples
  246
- Installation
  246
- S1D13505 Supported Evaluation Platforms
  246
- Usage
  246
- UTILITIES (X23A-B-001-02) EPSON 3-I
  246
- Comments
  247
- Program Messages
  247
- 13505Pwr Software Suspend Power Sequencing Utility
  248
- Installation
  248
- S1D13505 Supported Evaluation Platforms
  248
Section 4

252
- Features
  254
- Introduction
  254
- Cpu/Bus Interface Connector Pinouts
  257
- Host Bus Interface Pin Mapping
  259
- Clock Input Support
  260
- Decode Logic
  260
- DRAM Support
  260
- ISA Bus Support
  260
- Non-ISA Bus Support
  260
- Technical Description
  260
- Adjustable LCD Panel Negative Power Supply
  261
- Adjustable LCD Panel Positive Power Supply
  261
- Color Passive LCD Panel Support
  261
- Color TFT/D-TFD LCD Panel Support
  261
- CRT Support
  261
- Monochrome LCD Panel Support
  261
- Power Save Modes
  261
- Cpu/Bus Interface Header Strips
  262
- Schematic Notes
  262
- Parts List
  263
- Schematic Diagrams
  264
Section 5

269
- General Description
  272
- Interfacing the S1D13505 to the Pc Card Bus
  272
- Introduction
  272
- Register/Memory Mapping
  273
- Hardware Configuration
  274
- Performance
  274
- S1D13505 Configuration
  274
- Interfacing to the Nec V R 4102 Tm /V R 4111 Tm Microprocessor
  275
- Hardware Description
  276
- NEC V R 4102 TM /V R 4111 TM Configuration
  276
- S1D13505 Configuration
  276
- Interfacing to the Nec
  277
- Introduction
  277
- Nec V Rtm
  280
- S1D13505 Configuration
  280
- S1D13505 Pin Mapping
  280
- Interfacing to the Philips Mips Pr31500/Pr31700 Processor
  281
- Interfacing to the PR31500/PR31700
  281
- Introduction
  281
- PR31500/PR31700 Host Bus Interface Pin Mapping
  282
- PR31500/PR31700 Host Bus Interface Signals
  282
- S1D13505 Host Bus Interface
  282
- Direct Connection to the Philips PR31500/PR31700
  283
- Hardware Description
  283
- Memory Mapping and Aliasing
  285
- S1D13505 Configuration
  285
- Hardware Description
  286
- IT8368E Configuration
  286
- S1D13505 Configuration
  286
- System Design Using the IT8368E PC Card Buffer
  286
- Software
  287
- Interfacing to the Toshiba Mips Tx3912 Processor
  288
- Interfacing to the TX3912
  288
- Introduction
  288
- S1D13505 Host Bus Interface
  289
- TX3912 Host Bus Interface Pin Mapping
  289
- Direct Connection to the Toshiba TX3912
  290
- Hardware Description
  290
- TX3912 Host Bus Interface Signals
  290
- Memory Mapping and Aliasing
  292
- S1D13505 Configuration
  292
- Hardware Description
  293
- IT8368E Configuration
  293
- S1D13505 Configuration
  293
- System Design Using the IT8368E PC Card Buffer
  293
- Software
  294
- General Description
  295
- Introduction
  295
- Mmpc821 M
  295
- Hardware Connections
  296
- Hardware Configuration
  298
- S1D13505 Configuration
  298
- MPC821 Chip Select Configuration
  299
- Test Software
  300
- Test Software Source Code
  300
- Dac Application Notes
  301
- Introduction
  301
- Notes When Operating the S1D13505 Built-In DAC
  301
- DAC Isolated Power Source
  302
- Peripheral Circuit of DAC Pins
  303
- RED/GREEN/BLUE Pins
  304
- HRTC and VRTC Pins
  305
- IREF Pin
  305
- Isolated DAC Power Pin
  306
- Notes When the DAC Is Not Used
  306
- Isolated DAC Signal Pins
  307
- Power Consumption
  308
- S1D13505 Power Consumption
  308
- Conditions
  309
- Build for the Hitachi D9000 and ETMA ODO Evaluation Systems
  312
- Example Driver Builds
  312
- Program Requirements
  312
- Windows ® Ce Display Drivers
  312
- Build for CEPC (X86)
  314
- Example Installation
  316
- Installation for CEPC Environment
  316
- Installation for Hitachi D9000 and ETMA ODO
  316

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