Table 7-21: Power Save Mode Timing - Epson S1D13506 Technical Manual

Page 80
Symbol
t1 Power Save Mode Enable Bit high to FPFRAME inactive
t2 Power Save Mode Enable Bit low to FPFRAME active
Power Save Mode Enable Bit high to FPLINE, FPSHIFT, FPDATA,
t3
DRDY inactive
Power Save Mode Enable Bit low to FPLINE, FPSHIFT, FPDATA, DRDY
t4
active
t5 Power Save Mode Enable Bit high to LCD Power Save Status Bit high
t6 Power Save Mode Enable Bit low to LCD Power Save Status Bit low
Power Save Mode Enable Bit high to Memory Controller Power Save
t7
Status Bit high (self-refresh or no refresh selected)
Power Save Mode Enable Bit low to Memory Controller Power Save
t8
Status Bit low (self-refresh or no refresh selected)
Memory Controller Power Save Status Bit low to the earliest time where
t9
memory access is allowed (self-refresh or no refresh selected)
1. t7 = (1 DRAM refresh clock period) + 12 MCLK periods
max
S1D13506
X25B-A-001-12

Table 7-21: Power Save Mode Timing

Parameter
Note
Where T is the period of FPFRAME, T
FPFRAME
T is the period of the pixel clock, and T
PCLK
Note
The DRAM refresh clock period is programmed using REG[021h].
Epson Research and Development
Vancouver Design Center
Min
T
129T
128T 129T
FPFRAME
is the period of FPLINE,
FPLINE
is the period of the memory clock.
MCLK
Hardware Functional Specification
Max Units
+
FPFRAME
ns
T
FPLINE
3T ns
FPLINE
+
FPFRAME
ns
T
FPLINE
T ns
FPFRAME
ns
FPRAME
T ns
PCLK
note 1 ns
12T ns
MCLK
8T ns
MCLK
Issue Date: 02/03/26