Epson S1D13506 Technical Manual page 42

Page 36
Pin Name Type
58, 60, 62,
MA[8:0] O 64, 66, 67,
65, 63, 61
MA9 IO
MA10 IO
MA11 IO
S1D13506
X25B-A-001-12
Table 5-2: Memory Interface Pin Descriptions (Continued)
RESET#
Pin # Cell
State
CO1 0
a
0
56 C/TS1 or
b
Hi-Z
c
0
59 C/TS1 or
d
Hi-Z
e
0
or
f
57 C/TS1 Hi-Z
or
g
1
a
When the MD configuration at RESET# is set such that MA9 is used as MA9.
b
When the MD configuration at RESET# is set such that MA9 is used as GPIO3.
c
When the MD configuration at RESET# is set such that MA10 is used as MA10.
d
When the MD configuration at RESET# is set such that MA10 is used as GPIO1.
e
When the MD configuration at RESET# is set such that MA11 is used as MA11.
f
When the MD configuration at RESET# is set such that MA11 is used as GPIO2.
g
When the MD configuration at RESET# is set such that MA11 is used as VMPEPWR.
Multiplexed memory address - see Memory Interface Timing on page
70 for detailed functionality.
This is a multi-purpose pin:
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address bit 9
(MA9).
• For symmetrical 512K byte DRAM, this pin can be used as general
purpose IO pin 3 (GPIO3).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 10
(MA10).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
can be used as general purpose IO pin 1 (GPIO1).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 11
(MA11).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
can be used as general purpose IO pin 2 (GPIO2).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This pin can also be configured as the MediaPlug power pin
VMPEPWR - see Table 5-10:, "MA11, MA10, MA9, and DRDY Pin
Mapping," on page 43 for details.
Epson Research and Development
Vancouver Design Center
Description
Hardware Functional Specification
Issue Date: 02/03/26