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Page 10
Memory Tab
Access Time
Memory Type
WE# Control
S1D13506
X25B-B-001-02
The Memory tab contains settings that control the configuration of the DRAM used for the
S1D13506 display buffer.
Note
The DRAM memory type and access time determines the optimal memory clock
(MCLK). See "Clocks Tab" on page 12 for an explanation on how to determine the op-
timal memory clock.
Memory Configuration
Access Time
Memory Type
These four settings must be configured based on the
specification of the DRAM being used. For each of the
following settings refer to the DRAM manufacturer's
specification, unless otherwise noted.
Selects the access time of the DRAM.
The S1D13506 evaluation boards use 50ns DRAM.
Selects the memory type, either Extended Data Out
(EDO) or Fast Page Mode (FPM).
The S1D13506 evaluation boards use EDO DRAM.
Epson Research and Development
Vancouver Design Center
Refresh Time
Suspend Mode
Installed Memory
13506CFG Configuration Program
Issue Date: 01/03/14
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