Epson S1D13506 Technical Manual page 145

Epson Research and Development
Vancouver Design Center
LCD Vertical Non-Display Period Register
REG[03Ah]
LCD Vertical
Non-Display
n/a
Period Status
(RO)
bit 7
bits 5-0
Note
TFT FPFRAME Start Position Register
REG[03Bh]
n/a n/a
bits 5-0
Note
Hardware Functional Specification
Issue Date: 02/03/26
LCD Vertical LCD Vertical
Non-Display Non-Display
Period Bit 5 Period Bit 4
LCD Vertical Non-Display Period Status
This is a read-only status bit.
When a read from this bit = 1, a LCD panel vertical non-display period is occurring.
When a read from this bit = 0, the LCD panel output is in a vertical display period.
LCD Vertical Non-Display Period Bits [5:0]
These bits specify the LCD panel vertical non-display period height in 1 line resolution.
Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
TFT TFT
FPFRAME FPFRAME
Start Position Start Position
Bit 5 Bit 4
TFT FPFRAME Start Position Bits [5:0]
For TFT/D-TFD panel only, these bits specify the delay in lines from the start of the ver-
tical non-display period to the leading edge of the FPFRAME pulse.
FPFRAME start position in number of lines = (ContentsOfThisRegister) + 1
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
LCD Vertical LCD Vertical
Non-Display Non-Display
Period Bit 3 Period Bit 2
TFT TFT
FPFRAME FPFRAME
Start Position Start Position
Bit 3 Bit 2
Page 139
RW
LCD Vertical LCD Vertical
Non-Display Non-Display
Period Bit 1 Period Bit 0
RW
TFT TFT
FPFRAME FPFRAME
Start Position Start Position
Bit 1 Bit 0
S1D13506
X25B-A-001-12