Figure 3-8: Typical System Diagram (Pc Card Bus); Figure 3-9: Typical System Diagram (Philips Mips Pr31500/Pr31700 Bus) - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
PC Card
BUS
A[25:21]
A[20:1]
D[15:0]
WE#
CE2#
OE#
CE1#
WAIT#
RESET
PR31500
/PR31700
BUS
A[12:0]
D[23:16]
D[31:24]
ALE
/CARDREG
/CARDIORD
/CARDIOWR
/CARDxCSH
/CARDxCSL
/RD
/WE
/CARDxWAIT
DCLKOUT
RESET#

Figure 3-9: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)

Hardware Functional Specification
Issue Date: 02/03/26
Oscillator
VDD
A0
Decoder M/R#
Decoder
CS#
AB[20:1]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
RESET#
BUSCLK
Oscillator

Figure 3-8: Typical System Diagram (PC Card Bus)

M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
AB20
AB19
AB18
AB17
WE1#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPFRAME
S1D13506
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
.
Oscillator
Oscillator
FPDAT[7:4]
FPDAT[3:0]
FPFRAME
S1D13506
RED,GREEN,BLUE
1Mx16
FPM/EDO-DRAM
UD[7:0]
16-bit
LD[7:0]
Dual
FPSHIFT
FPSHIFT
LCD
FPFRAME Display
FPLINE
FPLINE
DRDY
DRDY (MOD)
GPIOx
CRT/TV
HRTC
Display
VRTC
IREF
IREF
UD[3:0]
8-bit
LD[3:0]
Dual
FPSHIFT
FPSHIFT
LCD
FPFRAME Display
FPLINE
FPLINE
DRDY DRDY (MOD)
GPIOx
CRT/TV
HRTC
Display
VRTC
IREF
IREF
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