Table 8-6: Crt/Tv Pclk Divide Selection; Table 8-7: Crt/Tv Pclk Source Selection; Table 8-8: Mediaplug Clock Divide Selection - Epson S1D13506 Technical Manual

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bits 5-4
CRT/TV PCLK Divide Select Bits
bits 1-0
CRT/TV PCLK Source Select Bits
MediaPlug Clock Configuration Register
REG[01Ch]
n/a n/a
bits 5-4
MediaPlug Clock Divide Select Bits
S1D13506
X25B-A-001-12
CRT/TV PCLK Divide Select Bits[1:0]
These bits determine the divide used to generate the CRT/TV pixel clock from the
CRT/TV pixel clock source.

Table 8-6: CRT/TV PCLK Divide Selection

00
01
10
11
CRT/TV PCLK Source Select Bits [1:0]
These bits determine the source of the CRT/TV pixel clock for the CRT/TV
display.

Table 8-7: CRT/TV PCLK Source Selection

00
01
10
11
Note
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
MediaPlug MediaPlug
Clock Divide Clock Divide
Select Bit 1 Select Bit 0
MediaPlug Clock Divide Select Bits[1:0]
These bits determine the divide used to generate the MediaPlug Clock from the CRT/TV
pixel clock source.

Table 8-8: MediaPlug Clock Divide Selection

00
01
10
11
Epson Research and Development
CRT/TV PCLK Source to CRT/TV PCLK
Frequency Ratio
1:1
2:1
3:1
4:1
CRT/TV PCLK Source
CLKI
BUSCLK
CLKI2
MCLK (see note)
n/a n/a
MediaPlug Clock Source to CRT/TV Pixel
Clock Frequency Ratio
1:1
2:1
3:1
4:1
Vancouver Design Center
RW
MediaPlug MediaPlug
Clock Source Clock Source
Select Bit 1 Select Bit 0
Hardware Functional Specification
Issue Date: 02/03/26