Table 7-2: Hitachi Sh-4 Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Clock frequency
CKIO
T Clock period
CKIO
t2 Clock pulse width low
t3 Clock pulse width high
t4 A[20:1], M/R#, RD/WR# setup to CKIO
t5 A[20:1], M/R#, RD/WR# hold from CSn#
t6 BS# setup
t7 BS# hold
t8 CSn# setup
t9 Falling edge RD# to D[15:0] driven
t10 CKIO to RDY# high
t11 Falling edge CSn# to RDY# driven
t12 CKIO to RDY# delay
t13 D[15:0] setup to 2
t14 D[15:0] hold (write cycle)
t15 D[15:0] valid to RDY# falling edge (read cycle)
t16 Rising edge RD# to D[15:0] tri-state (read cycle)
t17 CSn# high setup to CKIO
t18 Falling edge CKIO to RDY# tri-state
1. Two software WAIT states are required.
2. One software WAIT state is required.
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-2: Hitachi SH-4 Timing

Parameter
nd
CKIO after BS# (write cycle)
1
3.0V 5.0V
Min Max Min
0 66 0
1/f 1/f
CKIO CKIO
6 16
6 6
4 3
0 0
4 3
3 2
3 2
3 3
4 21 3
3 11 2
4 20 3
0 0
0 0
0 0
6 30 3
3 2
3 14 2
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2
Max Units
66 MHz
ns
ns
ns
ns
ns
ns
ns
ns
13 ns
7 ns
13 ns
ns
ns
ns
16 ns
ns
10 ns
S1D13506
X25B-A-001-12