Block Configuration; Reg (Registers); Synchronous Register Access (Write); Synchronous Register Access (Read) - Epson S2R72V18 Technical Manual

1.7.3

Block Configuration

The LSI CPUIF consists of four blocks: REG0, REG1, DMA0, and DMA1.
• REG0: Controls access to the register area
• REG1: Controls access to the register area
• DMA0: Port 0 DMA channel
• DMA1: Port 1 DMA channel
1.7.3.1

REG (Registers)

These control access to the LSI register areas. They include the following functions:
• Synchronous register access
• FIFO access
• RAM_Rd access
• Asynchronous register access
1.7.3.1.1

Synchronous Register Access (Write)

Writes data from an external bus to the register synchronized with the internal clock.
1.7.3.1.2

Synchronous Register Access (Read)

Outputs register data to an external bus with the read (asserted for both XCS and XRD) time
as the output enable period.
Significant registers with at least three bytes such as count values in the register read
operation include those that maintain the lower byte register value for the highest byte read
timing and output the value to an external bus when reading the lower byte to prevent an
incorrect count from being read – for example, due to carry-over of count values during the
access cycle.
S2R72V18 Technical Manual (Rev.1.00)
EPSON
1. Functions
163