Power Save Mode; Figure 7-21: Power Save Mode Timing - Epson S1D13506 Technical Manual

Epson Research and Development
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7.4.2 Power Save Mode

Power Save
Mode Enable Bit
(REG[1F0h] bit 0)
FPFRAME
FPLINE, FPSHIFT
FPDATA, DRDY
LCD Power Save
Status Bit
(REG[1F1h] bit 1)
Memory Controller
Power Save Status Bit
(REG[1F1h] bit 0)
Memory Access
Note
Note
Hardware Functional Specification
Issue Date: 02/03/26
t1
t3
t5
t7
allowed

Figure 7-21: Power Save Mode Timing

Memory accesses cannot be performed after a Power Save Mode has been initiated.
The Memory Controller Power Save Status Bit will go high only if the Refresh Select
Bits (REG[021h] bits 7-6) are set to Self-Refresh or No Refresh.
t6
t8
not allowed
t2
t4
t9
allowed
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