Table 8-3: Mclk Source Select; Md Configuration Readback Registers; Clock Configuration Registers - Epson S1D13506 Technical Manual

Page 128

8.3.3 MD Configuration Readback Registers

MD Configuration Status Register 0
REG[00Ch]
MD[7] MD[6]
Config. Status Config. Status
MD Configuration Status Register 1
REG[00Dh]
MD[15] MD[14]
Config. Status Config. Status
REG[00Ch] bits 7-0
REG[00Dh] bits 7-0

8.3.4 Clock Configuration Registers

Memory Clock Configuration Register
REG[010h]
n/a n/a
bit 4
bit 0
S1D13506
X25B-A-001-12
MD[5] MD[4]
Config. Status Config. Status
MD[13] MD[12]
Config. Status Config. Status
MD[15:0] Configuration Status Bits [15:0]
These read-only bits return the status of MD[15:0] at the rising edge of RESET#.
MCLK
n/a
Divide Select
MCLK Divide Select
When this bit = 1, the internal memory clock frequency is half of the MCLK source fre-
quency.
When this bit = 0, the memory clock frequency is equal to the MCLK source frequency.
The MCLK frequency should always be set to the maximum frequency allowed by the
DRAM. This provides maximum performance and minimizes overall system power
consumption.
MCLK Source Select
When this bit = 1, the source for the internal MCLK is derived from BUSCLK.
When this bit = 0, the source for MCLK is derived from CLKI.

Table 8-3: MCLK Source Select

MCLK Source Select
0
1
Note
The MCLK Divide Select bit must be set to 1 before changing the MCLK Source Select
bit.
Note
For further information on MCLK, refer to Section 20.2, "Clock Descriptions" on page
224.
MD[3] MD[2]
Config. Status Config. Status
MD[11] MD[10]
Config. Status Config. Status
n/a n/a
MCLK Source
CLKI
BUSCLK
Epson Research and Development
Vancouver Design Center
MD[1] MD[0]
Config. Status Config. Status
MD[9] MD[8]
Config. Status Config. Status
RW
MCLK Source
n/a
Select
Hardware Functional Specification
Issue Date: 02/03/26
RO
RO