Registers; Enabling The Lcd Panel; Disabling The Lcd Panel - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center

7.2.1 Registers

REG[040h] LCD Display Mode Register
LCD Display
n/a
Blank
Note

7.2.2 Enabling the LCD Panel

Note

7.2.3 Disabling the LCD Panel

Programming Notes and Examples
Issue Date: 02/03/21
SwivelView
n/a
Enable Bit 1
When set to 1, this bit disables the LCD display pipeline and forces all LCD data outputs
to zero. This effectively blanks the screen.
If a dual panel is used, the Dual Panel Buffer must be disabled before blanking the LCD
display. This is done by setting REG[041h] bit 0 to 1b.
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually enable
the LCD panel. In such a case, the following procedure applies.
1. Enable the LCD signals - Set REG[040h] = 0.
If a dual panel is used, enable the Dual Panel Buffer by setting REG[041h] bit 0 = 0b.
2. Enable GPIO1 to activate the LCD bias power.
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually disable
the LCD panel. In such a case, the following procedure applies.
1. Disable the LCD power using GPIO1.
2. Wait the required delay time for the LCD bias power supply to discharge.
3. Disable the LCD signals - Set REG[040h] = 1.
4. Disable the LCD pixel clock source if desired. (Optional)
LCD
n/a Bit-per-pixel
Select Bit 2
Page 39
LCD LCD
Bit-per-pixel Bit-per-pixel
Select Bit 1 Select Bit 0
S1D13506
X25B-G-003-04