Figure 20-1: Clock Selection - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
20 Clocks
20.1 Clock Selection
CLKI
BUSCLK
CLKI2
0
1
REG[010h] bit 0
Hardware Functional Specification
Issue Date: 02/03/26
The following diagram provides a logical representation of the S1D13506 internal clocks.
0
÷2
1
REG[010h] bit 4

Figure 20-1: Clock Selection

0
÷2
1
MD12 at RESET#
00
01
10
11
REG[014h] bits 1,0
REG[014h] bits 5,4
00
01
10
11
REG[018h] bits 1,0
REG[018h] bits 5,4
00
01
10
11
REG[01Ch] bits 1,0
REG[01Ch] bits 5,4
00
01
÷2
10
÷3
11
÷4
00
01
÷2
x2
10
÷3
Enable
÷4
11
REG[018h] bit 7
00
01
÷2
÷3 10
11
÷4
Page 223
BCLK
MCLK
LCD PCLK
CRT/TV
PCLK
MediaPlug
Clock
S1D13506
X25B-A-001-12