Memory Models; Display Buffer Location; Memory Organization For 4 Bpp (16 Colors/16 Gray Shades) - Epson S1D13506 Technical Manual

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3 Memory Models

3.1 Display Buffer Location

3.2 Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)

Bit 7 Bit 6
S1D13506
X25B-G-003-04
The S1D13506 is capable of several color depths. The memory model for each color depth
is packed pixel. The S1D13506 supports 4, 8, 15 and 16 bit-per-pixel (bpp) memory
models.
The S1D13506 supports either a 512k byte or 2M byte display buffer. The display buffer is
memory mapped and is accessible directly by software. The memory block location
assigned to the S1D13506 display buffer varies with each individual hardware platform.
For further information on the display buffer, see the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx.
Bit 5 Bit 4
Pixel 0
Bits 3-0
Figure 3-1: Pixel Storage for 4 Bpp in One Byte of Display Buffer
In this memory format each byte of display buffer contains two adjacent pixels. Setting or
resetting any pixel will require reading the entire byte, masking out the upper or lower
nibble (4 bits) and setting the appropriate bits to 1.
Four bit pixels provide 16 gray shades/color possibilities. For monochrome panels the gray
shades are generated by indexing into the first 16 elements of the green component of the
Look-Up Table (LUT). For color panels the 16 colors are derived by indexing into the first
16 positions of the LUT.
Epson Research and Development
Bit 3 Bit 2
Pixel 1
Bits 3-0
Programming Notes and Examples
Vancouver Design Center
Bit 1 Bit 0
Issue Date: 02/03/21