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S1D13503 Series
Epson S1D13503 Series Manuals
Manuals and User Guides for Epson S1D13503 Series. We have
2
Epson S1D13503 Series manuals available for free PDF download: Technical Manual
Epson S1D13503 Series Technical Manual (270 pages)
Graphics LCD Controller
Brand:
Epson
| Category:
Controller
| Size: 1.96 MB
Table of Contents
Table of Contents
11
Overview Description
17
Introduction
17
Scope
17
Technology
18
System
18
Display Modes
18
Features
18
Display Support
19
Power Management
19
Typical System Block Diagrams
20
16-Bit MC68000 MPU
20
Figure 1: 16-Bit 68000 Series
20
Figure 3: 16-Bit Mode, Example: I8086 (Maximum Mode)
21
Figure 2: 8-Bit Mode, Example: Z80
21
MPU with READY (or WAIT#) Signal
21
Figure 4: 8-Bit Mode (ISA)
22
Figure 5: 16-Bit Mode (ISA)
22
ISA Bus
22
Internal Block Diagram
23
Functional Block Descriptions
23
Bus Signal Translation
23
Control Registers
23
Sequence Controller
23
LCD Panel Interface
23
Figure 6: Internal Block Diagram
23
MPU / CRT Selector
24
SRAM Interface
24
Clock Inputs / Timing
24
Display Data Formatter
24
Address Generator
24
Data Bus Conversion
24
Memory Decoder
24
Port Decoder
24
Look-Up Table
24
Pinout Diagram
25
Figure 7: S1D13503 Pinout Diagram
25
Figure 8: S1D13503 Pinout Diagram
26
Figure 9: S1D13503 Pad Diagram
27
Table 4-1: PAD Coordinates
28
Table 5-1: Bus Interface
30
Pin Description
31
Description
32
Table 5-2: Display Memory Interface
32
Table 5-3: LCD Interface
33
Table 5-4: Clock Inputs
33
Table 5-5: Power Supply
33
Table 5-6: Summary of Power on / Reset Options
34
Table 5-7: I/O and Memory Addressing Example
34
Table 6-1: Absolute Maximum Ratings
35
Table 6-2: Recommended Operating Conditions
35
Table 6-3: Input Specifications
35
Table 6-4: Output Specifications
36
Table 7-1: IOW# Timing (MC68000)
37
Figure 10: IOW# Timing (MC68000)
37
Table 7-2: IOR# Timing (MC68000)
38
Figure 11: IOR# Timing (MC68000)
38
Table 7-3: MEMW# Timing (MC68000)
39
Figure 12: MEMW# Timing (MC68000)
39
Table 7-4: MEMR# Timing (MC68000)
40
Figure 13: MEMR# Timing (MC68000)
40
Non-MC68000, Mpu/Bus with READY (or WAIT#) Signal
41
Table 7-5: IOW# Timing (Non-MC68000)
41
Figure 14: IOW# Timing (Non-MC68000)
41
Table 7-6: IOR# Timing (Non-MC68000)
42
Figure 15: IOR# Timing (Non-MC68000)
42
Table 7-7: MEMW# Timing (Non-MC68000)
43
Figure 16: MEMW# Timing (Non-MC68000)
43
Table 7-8: MEMR# Timing (Non-MC68000)
44
Figure 17: MEMR# Timing (Non-MC68000)
44
Clock Input Requirements
45
Table 7-9: Clock Input Requirements
45
Figure 18: Clock Input Requirements
45
Recommended Clock Input
46
Figure 19: Recommended Clock Interface
46
Display Memory Interface Timing
47
Write Data to Display Memory
47
Table 7-10: Write Data to Display Memory
47
Figure 20: Write Data to Display Memory
47
Figure 21: Read Data from Display Memory
48
Table 7-11: Read Data from Display Memory
48
Read Data from Display Memory
48
LCD Interface
49
LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels
49
Figure 22: LCD Interface Timing - Monochrome Panel
49
Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel
50
LCD Interface Timing - 4-Bit Single Color Panel
52
Figure 23: LCD Interface Timing - 4-Bit Single Color Panel
52
Table 7-13: LCD Interface Timing - 4-Bit Single Color Panel
53
LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
54
Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
54
Table 7-14: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels
55
LCD Interface Timing - 16-Bit Single/Dual Color Panels
56
Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels
56
Table 7-15: LCD Interface Timing - 16-Bit Single/Dual Color Panels
57
Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1
58
LCD Interface Timing - 8-Bit Single Color Panels Format 1
58
Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1
59
LCD Interface Options
60
Figure 27: 4-Bit Single Monochrome Panel Timing
60
Figure 28: 8-Bit Single Monochrome Panel Timing
61
Figure 29: 8-Bit Dual Monochrome Panel Timing
62
Figure 30: 4-Bit Single Color Panel Timing
63
Figure 31: 8-Bit Single Color Panel Timing - Format 1
64
Figure 32: 8-Bit Single Color Panel Timing - Format 2
65
Figure 33: 8-Bit Dual Color Panel Timing
66
Figure 34: External Circuit Required for 16-Bit Panel
66
Figure 35: 16-Bit Single Color Panel Timing with External Circuit
67
Figure 36: 16-Bit Dual Color Panel Timing with External Circuit
68
Hardware Register Interface
69
Register Descriptions
69
Table 8-1: Gray Shade/Color Mode Selection
70
Table 8-2: LCD Data Width
71
Table 8-3: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface
72
Table 8-4: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface
72
Table 8-5: Power Save Mode Selection
72
Table 8-6: ID Bit Usage
78
Table 8-7: Look-Up Table Access
78
Look-Up Table Architecture
80
Gray Shade Display Modes
80
Table 8-8: Look-Up Table Configurations
80
Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture
80
Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture
81
Color Display Modes
82
Figure 39: 4-Level Color Mode Look-Up Table Architecture
82
Figure 40: 16-Level Color Mode Look-Up Table Architecture
83
Figure 41: 256-Level Color Mode Look-Up Table Architecture
84
Table 8-9: Power Save Mode Selection
85
Power Save Mode 1
85
Power Save Mode 2
85
Power Save Modes
85
Power Save Mode Function Summary
86
Pin States in Power Save Modes
86
Table 8-10: Power Save Mode Function Summary
86
Table 8-11: Pin States in Power Save Modes
86
Display Memory Interface
87
SRAM Configurations Supported
87
8-Bit Mode
87
Figure 42: 8-Bit Mode - 8K Bytes SRAM
87
Figure 43: 8-Bit Mode - 16K Bytes SRAM
87
Figure 44: 8-Bit Mode - 32K Bytes SRAM
88
Figure 45: 8-Bit Mode - 40K Bytes SRAM
88
16-Bit Mode
89
Figure 46: 8-Bit Mode - 64K Bytes SRAM
89
Figure 47: 16-Bit Mode - 16K Bytes SRAM
89
Figure 48: 16-Bit Mode - 64K Bytes SRAM
90
Figure 49: 16-Bit Mode - 128K Bytes SRAM
90
SRAM Access Time
91
8-Bit Display Memory Interface
91
Table 9-1: 8-Bit Display Memory Interface SRAM Access Time
91
Table 9-2: 16-Bit Display Memory Interface SRAM Access Time
91
Frame Rate Calculation
92
For Single Panel
92
For Dual Panel
92
Memory Size Calculation
93
Memory Size Requirement
93
Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640
93
Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480
94
Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320
94
Mechanical Data
95
Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503)
95
Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503)
96
This Page Left Blank
99
Introduction
105
Initializing the S1D13503
106
Gray Shades / Colors and Look-Up Tables
114
Memory Organization for One Bit Pixel (Black-And-White)
114
Memory Organization for Two Bit Pixels (4 Colors/Gray Shades)
114
Pixels
114
Memory Organization for Eight Bit Pixels (256 Colors)
115
Memory Organization for Four Bit Pixels (16 Colors/Gray Shades)
115
Look-Up Table (LUT)
116
LUT Registers
116
Look-Up Table Description
118
Black-And-White (One Bit/Pixel)
121
Four Gray Shades (Two Bits/Pixel in Monochrome Mode)
122
Four Colors (Two Bits/Pixel in Color Mode)
124
Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode)
126
Sixteen Colors (Four Bits/Pixel in Color Mode)
127
Colors (Eight Bits/Pixel in Color Mode)
128
Display Memory Models
130
Registers
130
Description
132
S5U13503B00C Evaluation Board Display Memory
132
Display Start Address Registers
133
Common Display Memory Requirements for LCD Panel Sizes
134
Advanced Techniques
136
Registers
136
Virtual Displays
136
Description
137
Bitmaps and Text Displays
138
Indexed Mapping
139
Mapping of Registers
139
Direct Mapping
140
Split Screen
141
Single Panel LCD
142
Dual Panel LCD
144
Initialization
148
Panning and Scrolling
148
Panning Right and Left
148
Scrolling up and down
149
Power Save Modes
150
Power Saving
150
Registers
150
Identifying the S1D13503
152
Programming the S1D13503
153
Main Loop Code
154
Initialization Code
156
Advanced Functions
162
Glossary
184
Table of Contents
213
Features
217
S5U13503B00C Rev 1.0 Evaluation Board
217
Installation and Configuration
218
ISA Bus Support
223
Technical Description
223
Monochrome LCD Support
224
Non-ISA Bus Support
224
SRAM Support
224
Adjustable LCD Panel Negative Power Supply
225
Adjustable LCD Panel Positive Power Supply
225
Color LCD Support
225
Power Save Modes
225
Cpu/Bus Interface Header Strips
226
Crystal Support
226
Oscillator Support
226
Schematic Notes
226
Appendix A Parts List
227
Appendix B S5U13503B00C Rev. 1.0 Schematic Diagrams
228
Table of Contents
241
Introduction
243
Reference Material
243
16-Bit Isa Bus Interface
244
Additional Discrete Logic Description
245
Configuration Options
245
PAL Equations
245
S1D13503 Default Setup
245
Register Setting
246
8-Bit Isa Bus Interface
247
Configuration Options
248
Register Setting
248
S1D13503 Default Setup
248
Introduction
253
Reference Material
253
Mc68340 Mpu Interface
254
MC68340 Setup
254
PAL Equations
255
S1D13503 Default Setup
255
Introduction
261
Reference Material
261
Configuration Equations
262
Example
262
Input Clock Requirement Calculation
262
Conclusions
263
SRAM Access Time
263
SRAM Size
263
SRAM Size and Access Time Requirements
263
16-Bit Display Memory Interface
264
Configuration Options
264
Implementation
264
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Epson S1D13503 Series Technical Manual (201 pages)
Dot Matrix Graphics LCD Controller
Brand:
Epson
| Category:
Controller
| Size: 1.89 MB
Table of Contents
Hardware Functional Specification
6
Hardware Functional Specification
4
Table of Contents
6
Introduction
11
Scope
11
Overview Description
11
Features
12
Technology
12
System
12
Display Modes
12
Display Support
13
Power Management
13
16-Bit MC68000 MPU
14
Figure 3-1 16-Bit 68000 Series (Example Implementation Only - Actual May Vary)
14
Figure 3-3 16-Bit Mode, Example: I8086 (Maximum Mode)
15
MPU with READY (or WAIT#) Signal
15
Figure 3-4 8-Bit Mode (ISA) (Example Implementation Only - Actual May Vary)
16
Figure 3-5 16-Bit Mode (ISA) (Example Implementation Only - Actual May Vary)
16
ISA Bus
16
Internal Block Diagram
17
Functional Block Descriptions
17
Bus Signal Translation
17
Control Registers
17
Figure 3-6 Internal Block Diagram
17
LCD Panel Interface
17
Look-Up Table
17
Memory Decoder
17
Port Decoder
17
Sequence Controller
17
Address Generator
18
Clock Inputs / Timing
18
Data Bus Conversion
18
Display Data Formatter
18
MPU / CRT Selector
18
SRAM Interface
18
Pinout Diagram
19
Figure 4-1 S1D13503F00A Pinout Diagram
19
Figure 4-2 S1D13503F01A Pinout Diagram
20
Figure 4-3 S1D13503D00A Pad Diagram
21
Description
23
Table 5-1 Bus Interface
23
Table 5-2 Display Memory Interface
24
Table 5-3 LCD Interface
24
Table 5-4 Clock Inputs
24
Table 5-5 Power Supply
24
Summary of Configuration Options
25
Table 5-6 Summary of Power on / Reset Options
25
Table 5-7 I/O and Memory Addressing Example
25
Table 6-1 Absolute Maximum Ratings
26
Table 6-2 Recommended Operating Conditions
26
Table 6-4 Output Specifications
27
Bus Interface Timing
28
Figure 7-1 IOW# Timing (MC68000)
28
IOW# Timing
28
MC68000 Interface Timing
28
Table 7-1 IOW# Timing (MC68000)
28
Figure 7-2 IOR# Timing (MC68000)
29
Figure 7-3 MEMW# Timing (MC68000)
29
IOR# Timing
29
MEMW# Timing
29
Table 7-2 IOR# Timing (MC68000)
29
Table 7-3 MEMW# Timing (MC68000)
29
Figure 7-4 MEMR# Timing (MC68000)
30
MEMR# Timing
30
Table 7-4 MEMR# Timing (MC68000)
30
Figure 7-5 IOW# Timing (Non-MC68000)
31
Figure 7-6 IOR# Timing (Non-MC68000)
31
Figure 7-7 MEMW# Timing (Non-MC68000)
31
IOR# Timing
31
IOW# Timing
31
MEMW# Timing
31
Non-MC68000, Mpu/Bus with READY (or WAIT#) Signal
31
Table 7-5 IOW# Timing (Non-MC68000)
31
Table 7-6 IOR# Timing (Non-MC68000)
31
Figure 7-8 MEMR# Timing (Non-MC68000)
32
MEMR# Timing
32
Table 7-7 MEMW# Timing (Non-MC68000)
32
Table 7-8 MEMR# Timing (Non-MC68000)
32
Clock Input Requirements
33
Figure 7-10 Recommended Clock Interface
33
Figure 7-9 Clock Input Requirements
33
Recommended Clock Input
33
Table 7-9 Clock Input Requirements
33
Display Memory Interface Timing
34
Figure 7-11 Write Data to Display Memory
34
Figure 7-12 Read Data from Display Memory
34
Read Data from Display Memory
34
Table 7-10 Write Data to Display Memory
34
Table 7-11 Read Data from Display Memory
34
Write Data to Display Memory
34
Figure 7-13 LCD Interface Timing - Monochrome Panel
35
LCD Interface
35
LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels
35
Table 7-12 LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel
36
Figure 7-14 LCD Interface Timing - 4-Bit Single Color Panel
37
LCD Interface Timing - 4-Bit Single Color Panel
37
Table 7-13 LCD Interface Timing - 4-Bit Single Color Panel
37
Figure 7-15 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels
38
LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels
38
Table 7-14 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels
38
Figure 7-16 LCD Interface Timing - 16-Bit Single/Dual Color Panels
39
LCD Interface Timing - 16-Bit Single/Dual Color Panels
39
Table 7-15 LCD Interface Timing - 16-Bit Single/Dual Color Panels
39
LCD Interface Timing - 8-Bit Single Color Panels Format 1
40
Figure 7-18 4-Bit Single Monochrome Panel Timing
41
Figure 7-19 8-Bit Single Monochrome Panel Timing
41
LCD Interface Options
41
Figure 7-20 8-Bit Dual Monochrome Panel Timing
42
Figure 7-21 4-Bit Single Color Panel Timing
42
Figure 7-24 8-Bit Dual Color Panel Timing
45
Figure 7-25 External Circuit Required for 16-Bit Panel
45
Figure 7-26 16-Bit Single Color Panel Timing with External Circuit
46
Figure 7-27 16-Bit Dual Color Panel Timing with External Circuit
47
Register Descriptions
48
Table 8-1 Gray Shade/Color Mode Selection
49
Table 8-3 Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface
51
Table 8-4 Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface
51
Table 8-5 Power Save Mode Selection
51
Table 8-6 ID Bit Usage
56
4-Level Gray Shade Mode
58
Figure 8-1 4-Level Gray-Shade Mode Look-Up Table Architecture
58
Figure 8-2 16-Level Gray-Shade Mode Look-Up Table Architecture
58
Gray Shade Display Modes
58
Look-Up Table Architecture
58
Table 8-8 Look-Up Table Configurations
58
4-Level Color Mode
59
Color Display Modes
59
Figure 8-3 4-Level Color Mode Look-Up Table Architecture
59
16-Level Color Mode
60
256-Level Color Mode
61
Figure 8-5 256-Level Color Mode Look-Up Table Architecture
61
Power Save Mode 1
62
Power Save Mode 2
62
Power Save Mode Function Summary
62
Power Save Modes
62
Table 8-10 Power Save Mode Function Summary
62
Table 8-9 Power Save Mode Selection
62
Pin States in Power Save Modes
63
Table 8-11 Pin States in Power Save Modes
63
Display Memory Interface
64
SRAM Configurations Supported
64
8-Bit Mode
64
Figure 9-1 8-Bit Mode - 8K Bytes SRAM (Requires AUX[01] Bit 0 = 0)
64
Figure 9-2 8-Bit Mode - 16K Bytes SRAM (Requires AUX[01] Bit 0 = 0)
64
Figure 9-3 8-Bit Mode - 32K Bytes SRAM (Requires AUX[01] Bit 0 = 1)
64
16-Bit Mode
65
Figure 9-4 8-Bit Mode - 40K Bytes SRAM [Either (8K × 8 + 32K × 8) Requiring AUX[01] Bit 0 = 0 or (32K × 8 + 8K × 8) Requiring AUX[01] Bit 0 = 1]
65
Figure 9-5 8-Bit Mode - 64K Bytes SRAM (Requires AUX[01] Bit 0 = 1)
65
SRAM Access Time
67
8-Bit Display Memory Interface
67
Frame Rate Calculation
67
For Dual Panel
67
For Single Panel
67
Table 9-1 8-Bit Display Memory Interface SRAM Access Time
67
Table 9-2 16-Bit Display Memory Interface SRAM Access Time
67
Memory Size Calculation
68
Memory Size Requirement
68
Mechanical Data
70
Programmer's Reference
74
Introduction
77
Initializing the S1D13503
78
Gray Shades / Colors and Look -U P Tables
84
Pixels
84
Memory Organization for Four Bit Pixels (16 Colors/Gray Shades)
84
Memory Organization for One Bit Pixel (Black-And-White)
84
Memory Organization for Two Bit Pixels (4 Colors/Gray Shades)
84
Memory Organization for Eight Bit Pixels (256 Colors)
85
Look-Up Table (LUT)
85
LUT Registers
85
Color Mode
87
Look-Up Table Description
87
Monochrome Mode
87
Black-And-White (One Bit/Pixel)
90
Four Gray Shades (Two Bits/Pixel in Monochrome Mode)
90
Four Colors (Two Bits/Pixel in Color Mode)
92
Figure 8-4 16-Level Color Mode Look-Up Table Architecture
93
Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode)
94
Sixteen Colors (Four Bits/Pixel in Color Mode)
95
Colors (Eight Bits/Pixel in Color Mode)
96
Registers
98
Description
100
S5U13503P00C Evaluation Board Display Memory
100
Display Start Address Registers
101
Common Display Memory Requirements for LCD Panel Sizes
102
Virtual Displays
103
Registers
103
Description
104
Bitmaps and Text Displays
105
Mapping of Registers
106
Direct Mapping
106
Indexed Mapping
106
Split Screen
107
Description
107
Registers
107
Single Panel LCD
107
Dual Panel LCD
109
Displaying a Single Image on a Dual Panel
112
Panning and Scrolling
114
Initialization
114
Panning Right and Left
114
Scrolling up and down
114
Power Saving
116
Power Save Mode 1
116
Power Save Mode 2
116
Power Save Mode Function Summary
116
Power Save Modes
116
Registers
116
Programming to Enter Power down Mode
117
Programming to Exit Power down Mode
117
Identifying the S1D13503
118
Programming the S1D13503
119
Main Loop Code
120
Initialization Code
122
Advanced Functions
127
Glossary
145
Utilities
148
13503Show.exe D Isplay Tility
149
13503Virt.exe Display Utility
151
13503Bios.com U Tility
153
13503Mode.exe D Isplay Tility
155
13503Pd.exe Power down Utility
157
13503Read.exe D Iagnostic Utility
159
S5U13503P00C Evaluation Board User's Manual
162
1 S5U13503P00C Rev 1.0 Evaluation Board
164
Features
164
2 Installation and Configuration
165
3 Technical Description
169
ISA Bus Support
169
Non-ISA Bus Support
170
SRAM Support
170
Monochrome LCD Support
170
Color LCD Support
171
Power Save Modes
171
Adjustable LCD Panel Negative Power Supply
171
Adjustable LCD Panel Positive Power Supply
171
Crystal Support
172
Oscillator Support
172
Cpu/Bus Interface Header Strips
172
Schematic Notes
172
APPENDIX A Parts List4-10
173
APPENDIX B S5U13503P00C Rev. 1.0 Schematic Diagrams
174
Application Notes
183
1 Isa Bus Interface Considerations
185
Introduction
185
Reference Material
185
16-Bit ISA Bus Interface
186
PAL Equations
186
Additional Discrete Logic Description
187
Configuration Options
187
Register Setting
187
S1D13503 Default Setup
187
8-Bit ISA Bus Interface
188
Configuration Options
188
Register Setting
188
S1D13503 Default Setup
188
2 Mc68340 Interface Considerations
189
Introduction
189
Reference Material
189
MC68340 MPU Interface
190
PAL Equations
190
Configuration Options
191
Register Setting
191
S1D13503 Default Setup
191
3 Lcd Panel Options / Memory Requirements
192
Introduction
192
Reference Material
192
Configuration Equations
193
Example
193
Input Clock Requirement Calculation
193
SRAM Size
193
SRAM Size and Access Time Requirements
193
SRAM Access Time
194
Conclusions
194
Implementation
194
16-Bit Display Memory Interface
194
Configuration Options
194
Register Settings
195
4 S1D13503 Power Consumption
197
Table 8-2 LCD Data Width
198
5 S1D13503 / Sed1352 Comparison
198
Feature Comparison
198
S1D13503 Register Changes / Additions from the SED1352
198
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