Memory Interface; Table 5-2: Memory Interface Pin Descriptions - Epson S1D13506 Technical Manual

Epson Research and Development
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5.2.2 Memory Interface

Pin Name Type Pin #
LCAS# O
UCAS# O
WE# O
RAS# O
34, 36, 38,
40, 42, 44,
46, 48, 49,
MD[15:0] IO
47, 45, 43,
41, 39, 37,
Hardware Functional Specification
Issue Date: 02/03/26

Table 5-2: Memory Interface Pin Descriptions

RESET#
Cell
State
51 CO1 1
52 CO1 1
53 CO1 1
54 CO1 1
Hi-Z
C/TS1D
(pull 0)
35
• For dual-CAS# DRAM, this is the column address strobe for the
lower byte (LCAS#).
• For single-CAS DRAM, this is the column address strobe (CAS#).
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
• For dual-CAS# DRAM, this is the column address strobe for the
upper byte (UCAS#).
• For single-CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
• For dual-CAS# DRAM, this is the write enable signal (WE#).
• For single-CAS# DRAM, this is the write enable signal for the lower
byte (LWE#).
See Table 5-8:, "Memory Interface Pin Mapping," on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
Row address strobe - see Memory Interface Timing on page 70 for
detailed functionality.
Bi-directional memory data bus.
During reset, these pins are inputs and their states at the rising edge of
RESET# are used to configure the chip - see Summary of
Configuration Options on page 39. Internal pull-down resistors (typical
values of 100KΩ/180ΚΩ at 5V/3.3V respectively) pull the reset states
to 0. External pull-up resistors can be used to pull the reset states to 1.
See Memory Interface Timing on page 70 for detailed functionality.
Description
X25B-A-001-12
Page 35
S1D13506