Epson S1D13506 Technical Manual page 300

Page 66
REG[10Ch] BitBLT Memory Address Offset Register 0
BitBLT BitBLT
Memory Memory
Address Address
Offset Bit 7 Offset Bit 6
REG[10Dh] BitBLT Memory Address Offset Register 1
n/a n/a
REG[110h] BitBLT Width Register 0
BitBLT Width BitBLT Width
Bit 7 Bit 6
REG[111h] BitBLT Width Register 1
n/a n/a
REG[112h] BitBLT Height Register 0
BitBLT Height BitBLT Height
Bit 7 Bit 6
REG[113h] BitBLT Height Register 1
n/a n/a
S1D13506
X25B-G-003-04
BitBLT BitBLT
Memory Memory
Address Address
Offset Bit 5 Offset Bit 4
n/a
The BitBLT Memory Address Offset Registers form the BitBLTs 11-bit address offset
from the starting word of line "n" to the starting word of line "n + 1". They are used for
address calculation only when the BitBLT is configured as a rectangular region of memory
using the BitBLT Destination/Source Linear Select bits (REG[100h] bits 1-0). They are not
used for the displays.
BitBLT Width BitBLT Width
Bit 5 Bit 4
n/a
The BitBLT Width Registers form a 10-bit register that specifies the BitBLT width in
pixels less 1.
Note
The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require
a BitBLT Width ≥ 2.
BitBLT Height BitBLT Height
Bit 5 Bit 4
n/a
The BitBLT Height Registers form a 10-bit register that specifies the BitBLT height in
pixels less 1.
BitBLT
Memory
Address
Offset Bit 3
n/a n/a
BitBLT Width BitBLT Width
Bit 3
n/a n/a
BitBLT Height BitBLT Height
Bit 3
n/a n/a
Epson Research and Development
Vancouver Design Center
BitBLT BitBLT
Memory Memory
Address Address
Offset Bit 2 Offset Bit 1
BitBLT BitBLT
Memory Memory
Address Address
Offset Bit 10 Offset Bit 9
BitBLT Width
Bit 2 Bit 1
BitBLT Width
n/a
Bit 9
BitBLT Height
Bit 2 Bit 1
BitBLT Height
n/a
Bit 9
Programming Notes and Examples
BitBLT
Memory
Address
Offset Bit 0
BitBLT
Memory
Address
Offset Bit 8
BitBLT Width
Bit 0
BitBLT Width
Bit 8
BitBLT Height
Bit 0
BitBLT Height
Bit 8
Issue Date: 02/03/21