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Epson S1R72V17 Connection Manual

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S1R72V17
CPU Connection Guide
Rev. 1.0

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Summary of Contents for Epson S1R72V17

  • Page 1 S1R72V17 CPU Connection Guide Rev. 1.0...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
  • Page 3 Scope This document applies to the S1R72V17 USB2.0 host/device controller LSI.

  • Page 4: Table Of Contents

    4. CPUIF Verification Procedure ......................10 5. Connection Example with FreeScale iMX21 ................. 14 Connection Example ........................ 14 iMX21 Bus Cycle Setting Example ................... 16 Checking S1R72V17 AC Spec and iMX21 Bus Cycle .............. 18 EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)

  • Page 5: Introduction

    1. Introduction Overview This document contains information required for actual use of the S1R72V17 by the customer, focusing on the details necessary to connect the S1R72V17 to the control CPU. This document describes typical connection methods. No guarantees are made regarding the suitability of these methods.

  • Page 6: Connection Example With Standard Cpu

    XWRH XWRH(XBEH) XWRL XWRL(XWR) XDREQ XDREQ *1 <When DMA is not used> XDACK XDACK *2 *1: Open XINT XINT *2: Fixed at High or Low Fig. 2-1 16-bit bus, Strobe mode connection example EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)
  • Page 7 CD[15:8] DATA[7:0] CD[7:0] XWRH(XBEH) XWRL(XWR) XDREQ XDREQ *1 <When DMA is not used> XDACK XDACK *2 *1: Open *2: Fixed at High or Low XINT XINT Fig. 2-3 8-bit bus mode connection example EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)

  • Page 8: Endian Settings For 16-Bit Bus Width Connection

    CPU_Endian bit. Access to Word register The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0] bus to the last byte of the Word register. The example below illustrates the writing and reading of 0x1234h data to/from the Word register.
  • Page 9 3. Endian Settings for 16-bit Bus Width Connection Access to Byte register The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus to the odd-number address register when the CPU_Endian bit is set to “0.”...
  • Page 10 3. Endian Settings for 16-bit Bus Width Connection Access to FIFO register The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus to the odd-number address register when the CPU_Endian bit is set to “0.”...

  • Page 11: Connection To Little-Endian Cpu

    CPU_Endian bit. Access to Word register The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0] bus to the last byte of the Word register. The example below illustrates the writing and reading of 0x1234h data to/from the Word register.
  • Page 12 3. Endian Settings for 16-bit Bus Width Connection Access to Byte register The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus to the odd-number address register when the CPU_Endian bit is set to “1.”...
  • Page 13 3. Endian Settings for 16-bit Bus Width Connection Access to FIFO register The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus to the odd-number address register when the CPU_Endian bit is set to “1.”...

  • Page 14: Cpuif Verification Procedure

    4. CPUIF Verification Procedure 4. CPUIF Verification Procedure The procedure shown here checks whether the S1R72V17 is correctly connected to the CPU. Follow the procedure given below, using ICE on the CPU used to control this LSI. <Connection test start (HW reset cancel)>...
  • Page 15 Little-endian CPU: 0x74h address Big-endian CPU: 0x75h address This register address is assigned to the 0x075h address. Since the S1R72V17 operates in the default big-endian state until this setting is changed, the 0x074h address should be accessed to access a little-endian CPU.
  • Page 16 4. CPUIF Verification Procedure Clock input setting Write the clock input setting value to the ClkSelect register (0x73h address). This sets the clock input method and frequency used for the S1R72V17. The settings are shown in Table 4-2. Table 4-2 ClkSelect register settings...
  • Page 17 These registers can be read/written in the Active state. The first bit (bit [7]) for the D_EPaIntEnb and D_EPbIntEnb registers cannot be written to and always reads “0.” <This ends the connection test.> EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)

  • Page 18: Connection Example With Freescale Imx21

    5. Connection Example with FreeScale iMX21 5. Connection Example with FreeScale iMX21 Connection Example This section illustrates an example of a connection between the proven CPU-IF on the S1R72V17 and the iMX21. The connection uses the S1R72V17 16-bit BE mode bus mode.
  • Page 19 Table 5-1 iMX21 shared pin settings iMX21 pin name iMX21 pin function NVDD1 to NVDD6 NVDD1 to NVDD6 A[8:1] A[8:1] D[15:0] D[15:0] OE/PC_IOWR EB3/DQM3/PC_IORD EB3 EB2/DQM2/PC_REG EB2 RW/PC_WE CSPI1_RDY EXT_DMAREQ LD16 EXT_DMAGRANT LD17 PA23(GPIO used as XINT) EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)

  • Page 20: Imx21 Bus Cycle Setting Example

    1'b1 EB3, 2 output mode for read (disabled) 3'b101 Data bus size (using 16 bits [15:0]) 4'b0000 CS1 output assert timing (0HCLK) CSEN 1'b1 CS1 enable (enabled) Fig. 5-2 Bus cycle setting registers EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)
  • Page 21 Bus cycle Write access WSC (8HCLK) HCLK bus clock A[8:1] (O) CS1　(O) CSA (0HCLK) CSN (0HCLK) RW　(O) RWA (2HCLK) RWN (1HCLK) WEA (0HCLK) EB3,2 (O) WEN (0HCLK) Fig. 5-3 iMX21 bus cycle waveform EPSON S1R72V17 CPU Connection Guide (Rev. 1.0)

  • Page 22: Checking S1R72V17 Ac Spec And Imx21 Bus Cycle

    5. Connection Example with FreeScale iMX21 Checking S1R72V17 AC Spec and iMX21 Bus Cycle The table below compares S1R72V17 AC specification values to iMX21 bus cycle settings. For more information on S1R72V17 AC specification, refer to “CPU/DMA IF Access Timing”...
  • Page 23 Revision History Revision History Revision details Date Rev. Page Type Details 06/06/2008 Newly created...
  • Page 24 Phone: +49-89-14005-0 FAX: +49-89-14005-110 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

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