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8 HARDWARE REGISTER INTERFACE
The SED1352 is configured and controlled via 15 internal 8-bit registers. There are two ways to map these registers into
the system I/O space.
1.
Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address
(where base I/O address is selected by VD7-VD12, see Table 5-6)
This scheme requires 16 sequential I/O addresses starting from the I/O mapped base address selected by VD7-VD12
(see Table 5-6).
To perform an I/O access:
write data
IOW {absolute I/O address}, {data}
read data
IOR {absolute I/O address}
2.
Indexing: I/O address = internal index register bits [3:0]
This scheme requires 2 sequential I/O addresses starting from the base address selected by VD4-VD12
(see Table 5-6).
To perform an 8-bit I/O access:
write index IOW {I/O mapped address}, {index}
then
write data
IOW {I/O mapped address +1}, {data}
or
read data
IOR {I/O mapped address +1}
To perform a 16-bit I/O access:
write data
IOW {I/O mapped address}, {index, data} ; write the index and data of the register to be accessed
read data
IOW {I/O mapped address}, {index}
IOR {I/O mapped address +1}
Note
Bits marked "n/o" should be set to 0 in the following registers.
8.1 Register Descriptions
AUX[00h] Test Register
I/O address = 0000b, Read/Write
Test Mode
Reserved
Enable
bit 7
Test Mode Enable
When this bit = 0 normal operation is enabled. When this bit = 1 the chip is placed in a special test mode.
The test input bits and test output bits (bits 6:0) are used to select various internal test functions.
bit 6
Reserved
During normal operation this bit must = 0.
bits 5-0
Test Mode Input Bits [2:0] and Output Bits [2:0]
When bit 7 = 1 these are the Test Input Select Input and Output bits. When bits 6 and 7 = 0 (normal opera-
tion) these bits may be used as read/write scratch registers.
SED1352
X16-SP-001-16
Test Input
Test Input
Select Bit 2
Select Bit 1
Epson Research and Development
; write the index of the register to be accessed
; write data to the indexed register
; read the indexed register
; write to the indexed register
; read the indexed register
Test Input
Test Output
Select Bit 0
Select Bit 2
Vancouver Design Center
Test Output
Test Output
Select Bit 1
Select Bit 0
Hardware Functional Specification
Issue Date: 99/07/28
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