Strongarm Sa-1110 To S1D13506 Interface; Hardware Description - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center

4 StrongARM SA-1110 to S1D13506 Interface

4.1 Hardware Description

SA-1110
VDDX
nOE
nWE
nCAS0
nCAS1
nCS4
A21
A[20:1]
D[15:0]
RDY
SDCLK2
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of SA-1110 to S1D13506 Interface
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
The S1D13506 is designed to directly support a variety of CPUs, providing an interface to
each processor's unique "local bus". Using the S1D13506's PC Card Host Bus Interface
provides a "glueless" interface to the SA-1110.
In this implementation, the address inputs (AB[20:1]) and data bus (DB[15:0]) connect
directly to the CPU address (A[20:1]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21.
BS# (Bus Start) is not used and should be tied high (connected to V
The following diagram shows a typical implementation of the SA-1110 to S1D13506
interface.
+3.3V
+3.3V
System RESET
+3.3V
Oscillator
Page 13
).
DD
S1D13506
VDD
RD#
WE0#
RD/WR#
WE1#
RESET#
BS#
CS#
M/R#
AB[20:1]
DB[15:0]
WAIT#
BUSCLK
CLKI
S1D13506
X25B-G-013-03