Epson S1R75801F00A Technical Manual
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Epson S1R75801F00A Technical Manual

Epson S1R75801F00A Technical Manual

Ieee1394 controller
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MF1447 - 02
IEEE1394 Controller
IEEE1394 Controller
S1R72803F00A
S1R75801F00A
Technical Manual
Technical Manual

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Summary of Contents for Epson S1R75801F00A

  • Page 1 MF1447 - 02 IEEE1394 Controller IEEE1394 Controller S1R75801F00A S1R72803F00A Technical Manual Technical Manual...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
  • Page 3 The information of the product number change Starting April 1, 2001 the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration of product number...

  • Page 4: Table Of Contents

    SPC7281F Contents 1. DESCRIPTION ..............................1 2. FEATURES ................................ 1 3. INTERNAL BLOCK DESCRIPTION ........................3 3.1 BLOCK DIAGRAM ............................. 3 3.2 BLOCK DIAGRAM DESCRIPTION ......................3 4. INTERNAL CONNECTION DIAGRAM ......................4 5. PIN ASSIGNMENT DIAGRAM .......................... 5 6. PIN DESCRIPTION ............................6 7.

  • Page 5: Description

    Ready for the data transfer rate of 100/200/400Mbps. Ready for isolation (bus holder integrated) IDE Interface Ready for the PIO mode 0/1/2/3/4, multi-word DMA mode 0/1/2, Ultra-DMA mode 0/1/2/3/4. Voltage level is 3.3V (TTL) level. 5V level input can be possible (5V Tolerant) EPSON...
  • Page 6 The CPU core built into this IC is an original 32-bit Programmable wait cycle (7 cycles, RISC CPU from SEIKO EPSON. Regarding the CPU Max.) core, refer to the S1C33208/204/202 Technical Manual Enables handshake through the and S1C33 Family ASIC Macro Manual.

  • Page 7: Internal Block Description

    -SBUS-. SRAM for the built-in memory area (Area 0). C33_PERI Block (C33 peripheral circuit block) Internal Flash Block The C33_PERI Block consists of the PSC (prescaler), Flash for the built-in memory area (Area 10). EPSON...

  • Page 8: Internal Connection Diagram

    SLEEP XCE8 HINTRQ xINT(K65) XCE6 SLEEP(P33) XWRL XWRH C33 Core BCLK XNMI U_AD<14:0> U_DT<15:0> X2SPDX xCSFREG ICEMD FLASH Controller xWRL DSIO OSC3 EXCLK_EN PLLC U_AD<14:0> PLLS1 U_DT<15:0> PLLS0 Flash ROM (64KB) EA10MD2 EA10MD1 EA10MD0 Fig. 4.1 Internal connection diagram EPSON...

  • Page 9: Pin Assignment Diagram

    S1R72803F00A 5. PIN ASSIGNMENT DIAGRAM N.C. N.C. XHRST HDD7 HDD8 HDD6 XWAIT HDD9 HDD5 HDD10 HDD4 HDD11 HDD3 HDD12 HDD2 EPSON HDD13 X2SPDX HDD1 RAMTST HDD14 PLLC HDD0 HDD15 S1R72803F00A PLLS0 HDMARQ PLLS1 XHIOW EA10MD0 XHIOR EA10MD1 HIORDY EA10MD2 TOP View...

  • Page 10: Pin Description

    IDE IORDY Signal 5V Tolerant, Drive Ability 2mA, Schmitt Input XHDMACK Hi-Z IDE DMA Acknowledge Signal 5V Tolerant, Drive Ability 2mA, Schmitt Input HINTRQ – IDE Interrupt Signal 5V Tolerant, Schmitt Input XHPDIAG – IDE PDIAG Signal 5V Tolerant, Schmitt Input EPSON...
  • Page 11 CPU Address Bus AD14 AD13 AD12 AD11 AD10 (LSB) DT15 Hi-Z (MSB) DT14 Hi-Z DT13 Hi-Z DT12 Hi-Z DT11 Hi-Z DT10 Hi-Z Hi-Z Hi-Z Hi-Z CPU Data Buss Pull Up Resistor Intgrated Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (LSB) EPSON...
  • Page 12 Serial I/O Pin for Debug: Pull Up Resister Integrated Use for communication with ICD33. Clock Generator Pin OSC3 MCU Clock Input Input Crystal Oscillator PLLS1 PLL Set Pin 1 Input PLLS0 PLL Set Pin 0 Input PLLC – Capacitor Connection Pin for PLL EPSON...
  • Page 13 N.C. Pin N.C. – – 2,45,48,91,94,137,140,172,183 (9 Pins) Table 6.1 Settings of EA10M2, EA10M1, and EA10M0 (Area 10 Boot Mode) P_EA10M2 P_EA10M1 P_EA10M0 Function Built-in Flash Boot Mode External ROM Mode Note) Other settings are not available on this IC. EPSON...

  • Page 14: Functional Description

    Flash ROM Control Register 0x200008 Reserved 0x300000 Area 6 Reserved 0x400000 Area 7 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM: 8KB) 0x402000 Reserved 0x600000 Area 8 Reserved 0x800000 Area 9 Reserved 0xC00000 Area 10 Internal Flash ROM (64KB) 0xC10000 External ROM (4MB) Reserved 0xFFFFFF EPSON...

  • Page 15: Ieee1394Link/Transaction Controller Xcsbuf Area (Sram)

    SBP2 Control Block, a PageTable fetch and data reception according to 1394 or IDE DMA, data transfer according to SBP-2 are executable by among the areas are guaranteed by hardware . (The hardware. size of each RingBuffer is variable by settings on the EPSON...

  • Page 16: Ieee1394 Packet Format

    Sbid (MSB) DestinationID (LSB) PacketTypeSpecInfo PacketTypeSpecQuadletData reserved – 1 QuadWriteReq (tcode : 0x0) DestinationID (MSB) (LSB) DestinationOffset QuadletData 2 QuadReadResp (tcode : 0x6) rcode DestinationID reserved QuadletData 3 BlockReadReq (tcode : 0x5) DestinationID (MSB) (LSB) DestinationOffset DataLength ExtendedTcode EPSON...
  • Page 17 All Other Value Reserved Sbid Souce Bus ID 0:3FFh, 1:Source ID Name Bit count Description Received AckCode 4'h1 ask_complete 4'h2 ask_pending 4'h4 ask_busy_X 4'h5 ask_busy_A 4'h6 ask_busy_B 4'hB ask_tardy 4'hC ask_confilict_error 4'hD ask_data_error 4'hE ask_type_error 4'hF ask_address_error All Other Value Reserved EPSON...

  • Page 18: Receive Packet Format

    BC 0 DestinationID tcode (MSB) SourceID (LSB) PacketTypeSpecInfo PacketTypeSpecQuadData reserved (tcode : 0x0) 1 QuadWriteReq SourceID (MSB) (LSB) DestinationOffset QuadletData (tcode : 0x6) 2 QuadReadResp rcode SourceID reserved QuadletData (tcode : 0x5) 3 BlockReadReq SourceID (MSB) (LSB) DestinationOffset DataLength ExtendedTcode EPSON...
  • Page 19 0 x 0 BT 0 reserved tcode (0xE) reserved PhyPacket reserved (5) SelfIDPacket Received SelfID packets between BusReset and 1st-ArbRstGap (tcode : 0xE) b.31 24 23 16 15 DataLength – BT 1 – reserved reserved tcode (0xE) *DataPointer reserved EPSON...
  • Page 20 Presence/absence of the Header CRC error (1: Packet disabled) Transmitted AckCode (Note 2) PSTS AckCode which was scheduled to be transmitted (Note 2) (Note 1) Refer to the Transmit Packet Common spd (speed code). (Note 2) Refer to the Transmit Packet Common Ack (AckCode). EPSON...

  • Page 21: Ieee1394 Hardware Sbp-2 Control

    (5) Reads and writes the data of data bus DD15-0 of IDE from and to the FIFO in the 1394LINKCORE by the XHIOR/XHIOW signal. If the FIFO becomes full or empty to disable data transfer, this block suspends data transfer with specified timing. EPSON...

  • Page 22: Flash Controller

    This IC is ready for the Sector Erase in the unit of You cannot change the data of the memory cell from 512 words/sector. “0” to “1” by writing. According to a specified sequence, you can erase all EPSON...

  • Page 23: Internal Register

    Priority Request Count Register 0x28 ChnlIndex ISO Async Stream Channel Index Register 0x29 ChnlWindow ISO Async Stream Channel Window Register 0x2A CmprIndex Compare Offset Address Index Register 0x2B CmpRW indow Compare Offset Address Window Register 0x2C CYCLE_TIME_H Cycle Time Register Higher Rank EPSON...
  • Page 24 Bus Reset Header Pointer Register Lower Rank 0x5A BRstORBPtr_H Bus Reset ORB Pointer Register Higher Rank 0x5B BRstORBPtr_L Bus Reset ORB Pointer Register Lower Rank 0x5C (Reserved) 0x5D (Reserved) 0x5E MaintCtl_H Maintenance Control Register Higher Rank 0x5F MaintCtl_L Maintenance Control Register Lower Rank EPSON...
  • Page 25 IDE Command Control Register 0x7A IDE_CS12 IDE Command Control Register 0x7B IDE_CS13 IDE Command Control Register 0x7C IDE_CS14 IDE Command Control Register 0x7D IDE_CS15 IDE Command Control Register 0x7E IDE_CS16 IDE Command Control Register 0x7F IDE_CS17 IDE Command Control Register EPSON...

  • Page 26: Register/Bit Table

    Read Data[7:0] 0x28 ChnlIndex Channel Index 0x29 ChnlWindow Channel Window 0x2A CmprIndex Compare Address Index 0x2B CmprWindow Compare Address Window 0x2C CYCLE_TIME_H Cycle Second[6:0] CycCnt[12] 0x2D CYCLE_TIME_MH Cycle Count[11:4] 0x2E CYCLE_TIME_ML Cycle Count[3:0] Cycle Offset[11:8] 0x2F CYCLE_TIME_L Cycle Offset[7:0] EPSON...
  • Page 27 Memory Map Area Index 0x56 AreaWindow_H (MSB) Memory Map Area Window 0x57 AreaWindow_L (LSB) 0x58 BRstHdrPtr_H BusReset Header Pointer[12:8] 0x59 BRstHdrPtr_L BusResetHeaderPointer[7:5] 0x5A BRstORBPtr_H BusResetORBPointer[12:8] 0x5B BRstORBPtr_L BusResetORBPointer[7:2] 0x5C (Reserved) 0x5D (Reserved) 0x5E MaintCtl_H E_Hcrc E_Dcrc No_Pkt F_Ack N_ack 0x5F MaintCtl_L Ack[7:0] EPSON...
  • Page 28 ReceiveChannel4 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x0D ReceiveChannel5 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x0E ReceiveChannel6 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x0F ReceiveChannel7 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 EPSON...
  • Page 29 RxORBAreaStart_H (MSB) RxORBAreaStart[12:8] RxORBAreaStart_L RxORBAreaStart[7:2] (LSB) 0x01 TxHdrAreaStart_H (MSB) TxHdrAreaStart[12:8] TxHdrAreaStart_L TxHdrAreaStart[7:2] (LSB) 0x02 TxStreamAreaStart_H (MSB) TxStreamAreaStart[12:8] TxStreamAreaStart_L TxStreamAreaStart[7:2] (LSB) 0x03 TxStreamAreaEnd_H (MSB) TxStreamAreaEnd[12:8] TxStreamAreaEnd_L TxStreamAreaEnd[7:2] (LSB) 0x04 RxStreamAreaStart_H (MSB) RxStreamAreaStart[12:8] RxStreamAreaStart_L RxStreamAreaStart[7:2] (LSB) 0x05 (Reserved) (Reserved) 0x0F (Reserved) EPSON...

  • Page 30: Register Map

    0: None 1: ArbtrationResetGapDetected 0x00 0x00 – 2: Phy_int R(W) 0: None 1: PHY Interrupt Detected 1: PhyWrDone R(W) 0: None 1: PHY Register Write Done 0: PhyRdDone R(W) 0: None 1: PHY Register Read Done 0x07 (Reserved) 0x00 0x00 – EPSON...
  • Page 31 R/W 0: Disable 1: Enable 6: EnArbGap R/W 0: Disable 1: Enable 0x00 0x00 – 2: EnPhy_int R/W 0: Disable 1: Enable 1: EnPhyWrDone R/W 0: Disable 1: Enable 0: EnPhyRdDone R/W 0: Disable 1: Enable 0x0F (Reserved) 0x00 0x00 – EPSON...
  • Page 32 0x03 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] 0x12 (Reserved) 0x00 0x00 – 0x13 (Reserved) 0x00 0x00 – 0x14 (Reserved) 0x00 0x00 – 0x15 (Reserved) 0x00 0x00 – 0x16 (Reserved) 0x00 0x00 – 0x17 (Reserved) 0x00 0x00 – EPSON...
  • Page 33 1: None IRM Node 6: WonIRM R(W) 0: Other Node 1: Self Node 5: IRMID[5] 4: IRMID[4] Physical ID of IRM Node 0x3F – 0x3F 3: IRMID[3] No exist IRM Node then IRMID= 0x3F 2: IRMID[2] 1: IRMID[1] 0: IRMID[0] EPSON...
  • Page 34 0x00 – 3: RdAdd[3] 2: RdAdd[2] PHY Register Read Address 1: RdAdd[1] 0: RdAdd[0] 0x27 PhyRdstat_L 7: RdDat[7] 6: RdDat[6] 5: RdDat[5] 4: RdDat[4] PHY Register Read Data 0x00 0x00 – 3: RdDat[3] 2: RdDat[2] 1: RdDat[1] 0: RdDat[0] EPSON...
  • Page 35 2: Cycle Offset[10] 1: Cycle Offset[9] 0: Cycle Offset[8] 0x2F CYCLE_TIME_L 7: Cycle Offset[7] 6: Cycle Offset[6] CYCLE_TIME.cycle_offset 5: Cycle Offset[5] 4: Cycle Offset[4] 0x00 – – 3: Cycle Offset[3] 2: Cycle Offset[2] 1: Cycle Offset[1] 0: Cycle Offset[0] EPSON...
  • Page 36 Write is valid. 0: Payload Size[8] } else { 0x37 PayloadSize_L 7: Payload Size[7] Write is invalid. 6: Payload Size[6] 5: Payload Size[5] 4: Payload Size[4] 0x00 0x00 – 3: Payload Size[3] 2: Payload Size[2] 1: Payload Size[1] 0: Payload Size[0] EPSON...
  • Page 37 PageTableAdrs4 7: PtAdress[15] 6: PtAdress[14] 5: PtAdress[13] 4: PtAdress[12] 0x00 0x00 – 3: PtAdress[11] 2: PtAdress[10] 1: PtAdress[9] 0: PtAdress[8] 0x3F PageTableAdrs5 7: PtAdress[7] 6: PtAdress[6] 5: PtAdress[5] 4: PtAdress[4] 0x00 0x00 – 3: PtAdress[3] 2: PtAdress[2] 1: PtAdress[1] 0: PtAdress[0] EPSON...
  • Page 38 0x00 0x00 3: PTDP[11] 2: PTDP[10] 1: PTDP[9] 0: PTDP[8] 0x47 LinkTxStreamPtr_L 7: PTDP[7] Current Transmit Packet Data Area Pointer 6: PTDP[6] 5: PTDP[5] 4: PTDP[4] 0x00 0x00 3: PTDP[3] 2: PTDP[2] Write is ignore Read is always zero EPSON...
  • Page 39 3: ITSP[11] 2: ITSP[10] 1: ITSP[9] 0: ITSP[8] 0x4F IDE_TxStreamPtr_L 7: ITSP[7] Transmit Packet Stream Data Area IDE Pointer 6: ITSP[6] 5: ITSP[5] 4: ITSP[4] 0x00 0x00 – 3: ITSP[3] 2: ITSP[2] Write is ignore Read is always zero EPSON...
  • Page 40 4: MemMapWindow[12] 0x00 0x00 – 3: MemMapWindow[11] 2: MemMapWindow[10] 1: MemMapWindow[9] 0: MemMapWindow[8] R/W Memory Map Area Window 0x57 AreaWindow_L 7: MemMapWindow[7] 6: MemMapWindow[6] 5: MemMapWindow[5] 4: MemMapWindow[4] 0x00 0x00 – 3: MemMapWindow[3] 2: MemMapWindow[2] 1: MemMapWindow[1] 0: MemMapWindow[0] EPSON...
  • Page 41 1: Tx Optional AckCode 0x00 0x00 – 3: N_ack R/W 0: 1: No Transmit AckPacket 0x5F MaintCtl_L 7: Ack[7] 6: Ack[6] 5: Ack[5] 4: Ack[4] R/W Optional AckCode 0x00 0x00 – 3: Ack[3] 2: Ack[2] 1: Ack[1] 0: Ack[0] EPSON...
  • Page 42 1: DIAG 0: DASP 0x67 IDE_DmaStat 7: FIFOCnt[2] 6: FIFOCnt[1] Indicate word count in FIFO 5: FIFOCnt[0] 0x00 0x00 – 1: DmaPause 0: IDE DMA not Pause 1: IDE DMA Pause 0: DmaRun 0: Not DMA 1: IDE DMA Running EPSON...
  • Page 43 1: CRC[9] 0: CRC[8] IDE CRC Data Register 0x6D IDE_CRC1 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 0x00 0x00 – 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] 0x6E IDE_TestIndex 0x00 0x00 – 0x6F IDE_TestWindow 7: 0x00 0x00 – EPSON...
  • Page 44 Logical Block Address(LBA) bit 16 – 23 0x76 IDE_CS06 Command Block Register Device/Head Register 0x00 0x00 0x00 – Logical Block Address(LBA) bit 24 – 27 0x77 IDE_CS07 Command Block Register Read : Status Register 0x00 0x00 0x00 – Write: Command Register EPSON...
  • Page 45 Read : Data Bus Hi – Impedance 0x00 0x00 – Write: Not Used 0x7E IDE_CS16 Control Block Register Read : Alternate Status 0x00 0x00 – Write: Device Control 0x7F IDE_CS17 Control Block Register Read : (obsolete) 0x00 0x00 – Write: Not Used EPSON...

  • Page 46: Detail Description Of Register

    When the INTRQ signal is asserted to the IDE I/F, this bit becomes “1”. Bit0 BusReset Detected When a BusReset signal is detected on the 1394 Serial Bus, this bit becomes “1”. When it issues a BusReset, this bit becomes “1” as well. EPSON...
  • Page 47 When an interrupt factor from the PHY status indicated on the PHYIntStat Register exists, this bit becomes “1”. Bit0 LINK DMA Interrupt Status When an interrupt factor exists in the internal DMA operation indicated on the DmaIntStat Register, this bit becomes “1”. Address Register Name Bit Symbol Description H.Rst S.Rst B.Rst 0x02 (Reserved) 0x00 0x00 – EPSON...
  • Page 48 When a Transmit packet is disabled by a BusReset before an Ack packet is returned at the time of Async packet transmission, this bit becomes “1”. Bit0 Transmit Async Packet Ack-code Missing When a Ack packet is not returned at the time of Async packet transmission, this bit becomes “1”. EPSON...
  • Page 49 When the Tcode in a received packet is invalid, this bit becomes “1”. Bit0 transmit Retry Exceeded If a transmit retry fails since the set value of the MaxRetry Register is exceeded when the RetryLimit Register is not zero or the MaxRetry Register is not 0 and this bit becomes “1”. EPSON...
  • Page 50 When the CYCLE_START_PACKET does not exist over two local cycle events, this bit becomes “1”. Bit0 CycleStartPkt Arbitration Failed When a CYCLE_START_PACKET cannot be transmitted before the SubActionGap after a local cycle event occurs, this bit becomes “1”. This bit is enabled when cmstr = “1”. EPSON...
  • Page 51 Bit0 PHY Register Read Done When read data is stored in the PHYRdStat Register at the time of read access of the PHY Register, this bit becomes “1”. Address Register Name Bit Symbol Description H.Rst S.Rst B.Rst 0x07 (Reserved) 0x00 0x00 – EPSON...
  • Page 52 Sub-Interrupt Enable Flag Register This register enables/disables an interrupt factor of the SubIntStat Register. Setting the corresponding bit to “1” enables an interrupt to the CPU. Address Register Name Bit Symbol Description H.Rst S.Rst B.Rst 0x0A (Reserved) 0x00 0x00 – EPSON...
  • Page 53 R/W 0: Disable 1: Enable 0: EnCycArbFail R/W 0: Disable 1: Enable LINK Core Interrupt Enable Flag Register 0 This register enables/disables an interrupt factor of the LINKIntStat0 Register. Setting the corresponding bit to “1” enables an interrupt to the CPU. EPSON...
  • Page 54 Makes setting to return an Ack_tardy as a Ack code when receiving an Async packet. 0: Usual Ack code 1: ack_tardy Bit0 Soft Reset Setting this bit to “1” initializes the interiors of the circuit. After initializing it, it is restored to “0”. EPSON...
  • Page 55 When the self node is Cycle Master capable and a root, this bit becomes “1”. If the self node does not become a root in the Self-ID processing when this bit is set after the Bus Reset, this bit is cleared. EPSON...
  • Page 56 This bit is set to “1” when the self node comes to Root in the Self-ID process after the bus is reset. Bit 0 Cable Power Status This bit indicates the status of Cable Power, which is updated in the PHY Status. “1” : Cable Power Status OK “0” : Cable Power Status NG EPSON...
  • Page 57 Busy is returned. When this register is “0”, the Dual Phase retry is ignored. 0x1C Bit7..5 Second_Limit[2:0] Set a Dual Phase Retry Time (Unit: second). 0x1C, 0x1D Cycle Limit[12:0] Sets a retry time at Cycle Limit [12:0] (Unit: 125µs). EPSON...
  • Page 58 Self-ID packet or topology map. Bit5..0 IRM ID[5:0] When the EnLrmDetect bit is “1”, the node ID of the Isochronous Resource Manager detected in the Self-ID period is set. When no node corresponding to the IRM exists, it indicates the 0x3F value. EPSON...
  • Page 59 When requesting the PHY Register for a register write, this bit is set to “1”. After the execution, it is automatically cleared. Bit5 Reserved Bit4 Reserved Bit3..0 PHY Access Register Set a register address to access the PHY Register. EPSON...
  • Page 60 6: RdDat[6] 5: RdDat[5] 4: RdDat[4] PHY Register Read Data 0x00 0x00 – 3: RdDat[3] 2: RdDat[2] 1: RdDat[1] 0: RdDat[0] PHY Register Read Status Register (Lower Rank) Bit7..0 PHY Read Data Indicate register data indicated in the PHY status. EPSON...
  • Page 61 ChannelAvailable This is a register to provide a channel number resource to be used when transferring isochronous and asynchronous stream. ReceiveChannel This is a register to set an ISO channel number to be received by this IC. EPSON...
  • Page 62 When the BlkWrAreaSet bit is “1” and a BlockWriteRequest packet having an Destination_Offset address same as a value set to this register is received, the received data of payload is received by the RxStreamArea. This address is valid when the BlkWrAreaSel bit of the AsyDmaCtl Register is “1”. EPSON...
  • Page 63 CYCLE_TIME. cycle.offset When the self node is a CYCLE TIMER and the DisCycTimer=“0”, it is incremented in a cycle of 24.576MHz. When the Cycle Offset reaches 3072, it is restored to 0 and then the Cycle Count is incremented. EPSON...
  • Page 64 If you read it, it indicates 0. Bit1 HwSBP2Pause SBP2Pause:1 (Pause) Set => Pauses the hwSBP2 processing in execution. If you read it, it indicates 0. Bit0 HwSBP2Start SBP2Start:1 (Start) Set => Starts the hwSBP2 processing. If you read it, it indicates 0. EPSON...
  • Page 65 It is cleared at the time of Reset. Writing to this bit is ignored.. Bit0 TranExec. • TranExec:0 (Stop) => Indicates a Transaction is completed. • TranExec:1 (Execute) => Indicates a Transaction is in execution. It is cleared at the time of Reset. Writing to this bit is ignored.. EPSON...
  • Page 66 • RxBroadCast:1 => Though a response packet receive was completed, it was a broadcast packet. Bit0 RxAckDataError • RxAckDataErr:1 => Though a response packet was received, it was a DataCRCError. It does not assert the interrupt signal SBP2Err. It is automatically cleared on completion of the Transaction. EPSON...
  • Page 67 This register functions as an Index Register and Window Register to set a register to use for the HwSBP2 processing. HwSBP2Index This register sets an index number to select a channel. HwSBP2Window This register indicates a window specified by the HwSBP2Index. EPSON...
  • Page 68 This is a register to set a transmit destination of the HwSBP2. Set a Bus ID (10 bits) and Node ID (6 bits). SplitTime Set a split timeout time of a transaction of the HwSBP2. SplitTime.Second: Set a value in second. SplitTime.CycleCount: Set a value in 125µs. (Set range: 0 to 0x1F3F) Setting of a value exceeding 0x1F3F is not possible. EPSON...
  • Page 69 Read: Indicates a new PageTable size based on the written data size. (The number of pages x 8 bytes) When it is not written, zero can be read if the HwSBP2 correctly finishes. The remaining table size can be read when it is in execution or it finishes incorrectly. EPSON...
  • Page 70 This register specifies an address specified by the ORB of the SBP2. It is automatically updated in execution of the HwSBP2. Page Table Offset Address Write: Sets a Destination_Offset_Address accessed by the HwSBP2. It is ignored in execution of the HwSBP2. Read: Indicates the PageTable address following one being processed by the HwSBP2. EPSON...
  • Page 71 RxORBdataArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always “0”. Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always “0”. Reading the higher order bytes holds the lower order bytes. Read the higher order bytes first, then the lower order bytes. EPSON...
  • Page 72 2 Kbytes, the higher order 3 bits are always “0”. Reading the higher order bytes holds the lower order bytes. Read the higher order bytes first, then the lower order bytes. This register is read-only. Writing is ignored. EPSON...
  • Page 73 This Used Receive ORB Data Pointer Register indicates the starting address of used ORB data of receive packet in the RxORBArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always “0”. Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always “0”. EPSON...
  • Page 74 Quadlet unit, the lower order 2 bits are always “0”. Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always “0”. Reading the higher order bytes holds the lower order bytes. Read the higher order bytes first, then the lower order bytes. EPSON...
  • Page 75 Writing “1” to this bit updates the value of LINKTxStreamPtr to the latest value. When the firmware transmits data, this bit confirms that the transmit is normally completed as an error recovery to update the LINKTxStreamPtr. Do not use this bit in execution of the HwSBP2. EPSON...
  • Page 76 RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed, the RxDMACtl.ForceBusy is cleared. EPSON...
  • Page 77 Transmits an Async packet. Writing “1” to this bit starts to transmit an Async packet. On completion of the transmission, it is automatically restored to “0”. If you read this bit, it always indicates “0” regardless of presence/absence of transmit. EPSON...
  • Page 78 Transmits an ISO packet. Writing “1” to this bit starts to transmit an ISO packet. On completion of the transmission, it is automatically restored to “0”. If you read this bit, it always indicates “0” regardless of presence/absence of transmit. EPSON...
  • Page 79 If you set this bit during receiving a packet, the packet operates to complete the reception regardless of to what extent the packet has been received. It means that a RxDmaCmp interrupt occurs if this packet has been correctly received. The Ack_busy is continuously returned to the subsequent receive packets. EPSON...
  • Page 80 This register is an Index Register and Window Register to set each area of a memory map. MemMapIndex Sets an index number to select a register to set the starting address of each area of a memory map. MemMapWindow Indicates a window specified by the MemMapWindow. EPSON...
  • Page 81 This Bus Reset Header Pointer Register holds the value of a PostRxHdrPtr when a bus reset occurs. When several bus resets occur, it is updated to the latest PostRxHdrPtr. This register is read-only and writing to this register is ignored. EPSON...
  • Page 82 Immediately after transmitting it, this bit is cleared to “0”. Bit3 No_Ack Writing “1” to this bit abandons the ACK packet to be generated next without transmitting it. Immediately after abandoning it, this bit is cleared to “0”. Bit2..0 Reserved EPSON...
  • Page 83 Swaps the higher order 8 bits and lower order 8 bits when using the interface at 16 bits width. The access order to an address of 0x70 of the IDE-CSO Register is reversed. SWAP:1 Transfers the higher order 8 bit data first. SWAP:0 Transfers the lower order 8 bit data first. Bit1::0 Reserved EPSON...
  • Page 84 Decides the minimum value of the negate period of the strobe signal when accessing the register area of the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns EPSON...
  • Page 85 Decides the minimum cycle time of the strobe signal when transferring Ultra-DMA data through the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns EPSON...
  • Page 86 Indicates the state of the HINTRQ signal by positive logic. Bit4 IORDY Indicates the state of the HIORDY signal by positive logic. Bit3::2 Reserved Bit1 DIAG Indicates the state of the XHPDIAG signal by positive logic. Bit0 DASP Indicates the state of the XHDASP signal by positive logic. EPSON...
  • Page 87 DmaPause:0 DMA is in execution. Bit0 DmaRun Indicates whether the DMA mode in execution is in execution or not. It is enabled when the DmaRun bit is “1”. DmaPause:1 DMA is in execution. DmaPause:0 DMA is not in execution. EPSON...
  • Page 88 If you set an odd byte to this register or the OddStart bit of the CONFIG0 Register when using the data port of the IDE bus based on word size, 1 byte is short at the first or last transfer. It is automatically padded by the IC (data is undefined). EPSON...
  • Page 89 IDE_CRC1 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 0x00 0x00 – 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] CRC Read Register This register indicates CRC calculation results when transferring data by the Ultra-DMA through the IDE interface. EPSON...
  • Page 90 When the Interlock bit is on or at the time of UltraDMA, the XHDMACK is negated at the time of HDMAQR off or on completion of transfer. Note that, for this reason, the CPU access is put in wait state. EPSON...
  • Page 91 0x00 – Write: Device Control 0x7F IDE_CS17 Control Block Register Read : (obsolete) 0x00 0x00 – Write: Not Used IDE Command Control Register This register is a Command Block Register that is the I/O port of the IDE interface. EPSON...

  • Page 92: Flash Rom Control Register

    Turn on one of Bit0, Bit1 or Bit2 to select a desired operation. Next, turn on bit7. Sequence to set a value on FlashCtlCnt_reg Turn on Bit7 and one of Bit0, Bit1 and Bit2. Next, set a value on the FlashCtlCnt_reg. EPSON...
  • Page 93 FlashCtlCnt_L (lower order byte). On completion of writing to the lower order byte, setting of this register is enabled. Pulse width (Default value) FlashChipErs: 40ns x 0x3FFFFF = 167.8ms FlashSctErs: 40ns x 0x0FFFFF = 41.9ms FlashWrEnb: 40ns x 0x000190 = 16.0µs EPSON...
  • Page 94 When setting it in the unit of byte, conform to the order of higher order byte - lower order byte. If you reverse the order, data cannot be correctly written. Writing to the lower order byte updates the Flash Address Register to the next write address. EPSON...

  • Page 95: Electrical Characteristics

    Output current/pin –30 °C Storage temperature –65 to 150 9.2 RECOMMENDED OPERATING CONDITION Item Symbol Min. Typ. Max. Unit Supply voltage Input voltage – – °C Operating temperature TOPr1 – °C Operating temperature when TOPr2 – writing to FLASH ROM EPSON...

  • Page 96: Dc Characteristics (According To Recommended Operating Condition)

    – – IH1L LOW level input voltage V =3.0V – – IL1L Schmitt input characteristics (TTL) HIGH level trigger voltage V =5.5V – =3.6V LOW level trigger voltage V =4.5V – T2– =3.0V Hysteresis voltage =4.5V – – =3.0V EPSON...
  • Page 97 Unit Output characteristics Pin name: XHCS1, XHCS0, HDA2, HDA1, HDA0, XHPDIAG, HINTRQ, XHDMACK, HIORDY, XHIOR, XHIOW, HDMARQ, HDD15...0, XHRST HIGH level output voltage LV =3.0V – – =–2mA –0.4 LOW level output voltage LV =3.0V – – +0.4 =2mA EPSON...

  • Page 98: Ac Characteristics

    9.4 AC CHARACTERISTICS 9.4.1 Clock Timing 9.4.1.1 SCLK Timing SCLK 9.4.1.2 HCLK Timing HCLK Symbol Description Unit Min. Max. 49.152MHz ± 100ppm SCLK frequency SCLK duty cycle SCLK start → HCLK start delay time HCLK frequency 24.576 HCLK duty cycle EPSON...

  • Page 99: Phy-Link Interface Timing

    SCLK rising edge → C, Ctl, LReq delay time (Outputting) SCLK rising edge → C, Ctl, LReq delay time (When output ends.) Symbol Description Unit Min. Max. SCLK rising edge → C, Ctl set-up time SCLK rising edge → C, Ctl hold time EPSON...

  • Page 100: Ide Interface Timing

    XHIOR negate pulse time (NP+2)×20 XHIOR ↑→ XHCS0 ↑ – – XHIOR hold time HDD→ XHIOR ↑ – – Data set-up time XHIOR ↑→ HDD – – Data hold time HIORDY assert → XHIOR ↑ – – XHDMACK set-up time EPSON...
  • Page 101 XHIOW negate pulse width – (NP+2)×20 – XHIOW ↑→ XHCS0 ↑ XHIOW hold time – – XHIOW ↓→ HDD Data output delay time – XHIOW ↑→ HDD Data bus negate time – HIORDY assert → XHIOW ↑ XHDMACK set-up time – – EPSON...
  • Page 102 XHIOR assert pulse width (AP+2)×20 XHIOR ↑→ XHIOR ↓ – – XHIOR negate pulse width (AP+2)×20 XHIOR ↑→ XHDMACK ↑ XHIOR hold time – – HDD→ XHIOR ↑ Data set-up time – – XHIOR ↑→ HDD Data bus hold time – – EPSON...
  • Page 103 – (AP+2)×20 – XHIOW ↑→ XHIOW ↓ XHIOW negate pulse width – (AP+2)×20 – XHIOW ↑→ XHDMACK ↑ XHIOW hold time – – XHIOW ↓→ HDD Data output delay time – XHIOR ↑→ HDD Data bus negate time – EPSON...
  • Page 104 Data setup time – – HIORDY → HDD Data hold time – – HIORDY → HIORDY HIORDY cycle time – – HIORDY → HIORDY HIORDY cycle time x 2 – – XHIOR ↑→ HIORDY Last strobe time – – EPSON...
  • Page 105 XHDMACK ↓→ XHCS0,1 XHDMACK hold time – – HDD(CRC)→ HDMACK ↑ CRC data setup time – – HDMACK ↑→ HDD(CRC) CRC data hold time – – HDMARQ ↑→XHIOR ↓ Constrained interlock time – HIORDY→ HDMACK Minimum interlock time – – EPSON...
  • Page 106 HDD → XHIOR Data setup time – – XHIOR → HDD Data hold time – – XHIOR → XHIOR XHIOR cycle time – – XHIOR → XHIOR XHIOR cycle time x 2 – – HIORDY↑→ XHIOR Last strobe time – – EPSON...
  • Page 107 XHDMACK ↑→ HDD(CRC) CRC data hold time – – XHDMACK ↑→XHCS0,1 XHDMACK hold time – – HIORDY ↑→XHIOR Last strobe time – – HDMAQ ↓→ XHIOW Constrained interlock time – XHIOW ↑→ XHDMACK ↑ Minimum interlock time – – EPSON...

  • Page 108: Cpu Interface Timing

    – Read address access time (1) – (1+WC)–20 ACC1 Chip enable access time (1) – (1+WC)–20 CEAC1 Read signal access time (1) – (0.5+WC)–20 RDAC1 =40ns when bus clock is 25MHz in X2 mode. * WC: Wait cycle signal EPSON...
  • Page 109 In the built-in CPU core, however, a DMA controller or A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in the Technical Manual and Macro Manual. Both low- speed oscillation circuit (OSC1) and high-speed oscillation circuit (OSC4) are not available. EPSON...

  • Page 110: Examples Of External Connection For Reference Purposes

    S1R72803F00A 10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES EPSON...
  • Page 111 S1R72803F00A EPSON...
  • Page 112 JUMP-3 0.1u TC551664BFT Note: The circuit of this sheet is an example of connection when an external ROM and SRAM are connected during the process of system development. This circuit is not required on a system of finished product. EPSON...

  • Page 113: Shape Of Package

    S1R72803F00A 11. SHAPE OF PACKAGE Plastic QFP20-184 pin –0.4 –0.1 INDEX +0.05 0.16 —0.03 +0.05 0.125 —0.025 0¡ 10¡ –0.2 EPSON...
  • Page 114 101 Virginia Street, Suite 290 Telex : 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. Phone : +1-815-455-7630 Fax : +1-815-455-7633 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Northeast Taipei 110 301 Edgewater Place, Suite 120...
  • Page 115 S1R72803F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com/ First issue September,2001 Printed June, 2003 in Japan H A...

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