Epson S1D13506 Technical Manual page 403

Epson Research and Development
Vancouver Design Center
13506CFG Configuration Program
Issue Date: 01/03/14
The S1D13506 may use as many as three input clocks or as few as one. The more clocks
used the greater the flexibility of choice in display type and memory speed.
CLKI
CLKI2
BUSCLK
BCLK=BUSCLK/2
This setting determines the frequency of CLKI. CLKI is
typically used for the panel and CRT/TV pixel clocks.
Select "Auto" to have the CLKI frequency determined
automatically based on settings made on other configu-
ration tabs. After completing the other configurations,
the required CLKI frequency will be displayed in blue
in the Auto section.
If the CLKI frequency must be fixed to a particular rate,
set this value by selecting a preset frequency from the
drop down list or entering the desired frequency in
MHz.
This setting determines the frequency of CLKI2. If the
MediaPlug interface is required, CLKI2 is typically
used as the clock source.
Select "Auto" to have the CLKI2 frequency determined
automatically based on settings made on other configu-
ration tabs. After completing the other configurations,
the required CLKI2 frequency will be displayed in blue
in the Auto section.
If the CLKI2 frequency must be fixed to a particular
rate, set this value by selecting a preset frequency from
the drop down list or entering the desired frequency in
MHz.
This setting determines the frequency of the bus
interface clock (BUSCLK). This value is required for
calculating internal divisors which will yield the best
performance.
The BUSCLK frequency must be fixed to a particular
rate. Set this value by selecting a preset frequency from
the drop down list or entering the desired frequency in
MHz.
Indicates the BCLK to BUSCLK ratio. This ratio is set
at RESET# by the configuration pin CONF5.
Under normal circumstances BCLK = BUSCLK. This
option is only for configuring Toshiba/Philips inter-
faces when DCLKOUT is connected to the S1D13506
BUSCLK signal.
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S1D13506
X25B-B-001-02