Table 7-34: Crt A.c. Timing; Figure 7-49: Crt A.c. Timing - Epson S1D13506 Technical Manual

Page 118
VRTC
HRTC
Symbol
t1 VRTC cycle time
t2 VRTC pulse width low
t3 VRTC falling edge to FPLINE falling edge phase difference
1. t1 = [((REG[057h] bits 1:0, REG[056h] bits 7:0) + 1) + ((REG[058h] bits 6:0) + 1)] lines
2. t2 = [((REG[05Ah] bits 2:0) + 1)] lines
3. t3 = [((REG[053h] bits 5:0) + 1) × 8] Ts
S1D13506
X25B-A-001-12
t2
t3

Figure 7-49: CRT A.C. Timing

Table 7-34: CRT A.C. Timing

Parameter
Epson Research and Development
t1
Min.
Typical
Setting
2 note 1
1 note 2
8 note 3
Hardware Functional Specification
Vancouver Design Center
Max.
Units
Setting
1152 lines
8 lines
512 Ts
Issue Date: 02/03/26