Vr4102/Vr4111 To S1D13506 Interface; Hardware Description - Epson S1D13506 Technical Manual

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4 VR4102/VR4111 to S1D13506 Interface

4.1 Hardware Description

NEC V 4102/V
R R
WR#
SHB#
RD#
LCDCS#
LCDRDY
ADD[25:0]
DAT[15:0]
BUSCLK
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: NEC V
S1D13506
X25B-G-007-02
The NEC V 4102/V 4111 Microprocessors are specifically designed to support an external
R R
LCD controller. They provide the necessary internal address decoding and control signals.
The diagram below shows a typical implementation utilizing the S1D13506.
4111
4102/V
R
Note
For pin mapping see Table 3-1:, "Host Bus Interface Pin Mapping," on page 10.
Pull-up
System RESET
ADD21
4111 to S1D13506 Configuration Schematic
R
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Epson Research and Development
Vancouver Design Center
S1D13506
WE0#
WE1#
RD#
CS#
WAIT#
RESET#
M/R#
AB[20:0]
DB[15:0]
BUSCLK
V
DD
BS#
V
DD
RD/WR#
Issue Date: 01/02/08