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7.1.8 PC Card Timing (e.g. StrongARM)
CLK
(provided externally)
A[20:1]
M/R#
CE1#, CE2#
CS#
OE#
WE#
WAIT#
D[15:0](write)
D[15:0](read)
S1D13506
X25B-A-001-12
T
t2
t3
CLK
t4
t7
t11
Figure 7-8: PC Card Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
t9
Epson Research and Development
Vancouver Design Center
t5
t6
t8
t10
t13
t12
Hardware Functional Specification
Issue Date: 02/03/26