S1D13506 Host Bus Interface; Host Bus Interface Pin Mapping - Epson S1D13506 Technical Manual

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3 S1D13506 Host Bus Interface

3.1 Host Bus Interface Pin Mapping

S1D13506
X25B-G-007-02
The S1D13506 directly supports multiple processors. The S1D13506 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the
VR4102/VR4111 microprocessor.
The MIPS/ISA Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, "S1D13506 Hardware Configu-
ration" on page 13.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB20
AB[19:0]
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
NEC VR4102/VR4111 Pin Name
ADD20
ADD[19:0]
DAT[15:0]
SHB#
ADD21
LCDCS#
BUSCLK
V
DD
V
DD
RD#
WR#
LCDRDY
connected to system reset
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/08