Strongarm Sa-1110 Register Configuration - Epson S1D13506 Technical Manual

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4.5 StrongARM SA-1110 Register Configuration

Table 4-3: RDFx Parameter Value versus CPU Maximum Frequency
S1D13506
X25B-G-013-03
The SA-1110 requires configuration of several of its internal registers to interface to the
S1D13506 PC Card Host Bus Interface.
• The Static Memory Control Registers (MSC[2:0]) are read/write registers containing
control bits for configuring static memory or variable-latency IO devices. These regis-
ters correspond to chip select pairs nCS[5:4], nCS[3:2], and nCS[1:0] respectively. Each
of the three registers contains two identical CNFG fields, one for each chip select within
the pair. Since only nCS[5:3] controls variable-latency IO devices, MSC2 and MSC1
should be programmed based on the chip select used.
Parameter RTx<1:0> should be set to 01b (selects variable-latency IO mode).
Parameter RBWx should be set to 1 (selects 16-bit bus width).
Parameter RDFx<4:0> should be set according to the maximum desired CPU
frequency as indicated in the table below.
CPU Frequency
147.5MHz
206.4MHz
Up to SA-1110 maximum
Parameter RDNx<4:0> should be set to 0 (minimum command precharge time).
Parameter RRRx<2:0> should be set to 0 (minimum nCSx precharge time).
• The S1D13506 endian mode is set to little endian. To program the SA-1110 for little
endian as well use the control register (register 1).
• Bit 7 must be set to 0.
• The BUSCLK signal input to the S1D13506 (from one of the SDCLK[2:1] pins) is a
derivative of the SA-1110 internal processor speed. Since the PC Card Host Bus Inter-
face on the S1D13506 has a maximum BUSCLK of 50MHz, the output clock from the
SA-1110 must be a divided down from the processor clock. The DRAM Refresh
Control Register (MDREFR) determines the output of this signal.
• If SDCLK2 is used, bit 26 should be set to 1 to divide the CPU clock by 4.
• If SDCLK1 is used, bit 22 should be set to 1 to divide the CPU clock by 4.
Epson Research and Development
Vancouver Design Center
RDFx
2
3
4
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08