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Epson S1D13504 Technical Manual

Color graphics lcd/crt controller.
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S1D13504 Color Graphics LCD/CRT Controller
S1D13504
TECHNICAL MANUAL
Document Number: X19A-Q-002-14
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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   Summary of Contents for Epson S1D13504

  • Page 1

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 2

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 TECHNICAL MANUAL X19A-Q-002-14 Issue Date: 01/04/18...

  • Page 3

    Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics.

  • Page 4

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 TECHNICAL MANUAL X19A-Q-002-14 Issue Date: 01/04/18...

  • Page 5

    February 2001 DESCRIPTION The S1D13504 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system.

  • Page 6

    Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.

  • Page 7

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 8

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 9: Table Of Contents

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ..........11 Scope .

  • Page 10: Table Of Contents

    Page 4 Epson Research and Development Vancouver Design Center 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) ......38 7.1.3...

  • Page 11: Table Of Contents

    Epson Research and Development Page 5 Vancouver Design Center 8.2.9 External RAMDAC Control Registers ......111 Display Buffer .

  • Page 12: Vancouver Design Center

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 13

    S1D13504 Series Package list ........

  • Page 14

    S1D13504 Addressing ........

  • Page 15

    Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM ....14 Figure 3-2: Typical System Diagram –...

  • Page 16

    Page 10 Epson Research and Development Vancouver Design Center Figure 7-33: Dual Color 8-Bit Panel Timing ........78 Figure 7-34: Dual Color 8-Bit Panel A.C.

  • Page 17: Introduction

    The S1D13504 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system.

  • Page 18: Features

    Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Memory Interface • 16-bit DRAM interface: • EDO-DRAM up to 40MHz data rate (80M bytes per second). • FPM-DRAM up to 25MHz data rate (50M bytes per second).

  • Page 19: Display Modes

    • The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight – its power-on polarity is selected by an MD configuration pin. 2.7 Package and Pin Table 2-1: S1D13504 Series Package list Name Package S1D13504F00A...

  • Page 20: Typical System Implementation Diagrams

    Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Power Oscillator Management SH-3 M/R# CSn# A[20:0] AB[20:0] FPDAT[15:8] UD[7:0] D[15:0] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT WE1# WE1# S1D13504 Display FPFRAME FPFRAME RD/WR# RD/WR# FPLINE...

  • Page 21

    Epson Research and Development Page 15 Vancouver Design Center Power Oscillator Management MC68030 A[31:21] M/R# Decoder FC0, FC1 Decoder A[20:0] AB[20:0] FPDAT[15:8] UD[7:0] D[31:16] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT WE1# S1D13504 Display FPFRAME FPFRAME R/W# RD/WR# FPLINE FPLINE SIZ1...

  • Page 22: Block Description

    Page 16 Epson Research and Development Vancouver Design Center 4 Block Description 4.1 Functional Block Diagram 16-bit FPM/EDO DRAM Memory Power Save Register Controller Clocks Display Host FIFO Data CPU / MPU Look-Up Table Control CRTC Bus Clock Memory Clock...

  • Page 23: Functional Block Descriptions

    Epson Research and Development Page 17 Vancouver Design Center 4.2 Functional Block Descriptions 4.2.1 Host Interface The Host Interface block provides the means for the CPU/MPU to communicate with the display buffer and internal registers, via one of the supported bus interfaces.

  • Page 24: Pinout Diagram For S1d13504f00a

    Page 18 Epson Research and Development Vancouver Design Center 5 Pin Out 5.1 Pinout Diagram for S1D13504F00A 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...

  • Page 25: Pinout Diagram For S1d13504f01a

    Epson Research and Development Page 19 Vancouver Design Center 5.2 Pinout Diagram for S1D13504F01A 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 72 71 70 69 68 67 66 65...

  • Page 26: Pinout Diagram For S1d13504f02a

    Page 20 Epson Research and Development Vancouver Design Center 5.3 Pinout Diagram for S1D13504F02A 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73...

  • Page 27: Pin Description

    Epson Research and Development Page 21 Vancouver Design Center 5.4 Pin Description Key: Input Output Bi-Directional (Input/Output) Power pin CMOS level input CMOS level input with pull-down resistor (typical values of 100KΩ/180KΩ at 5V/3.3V respectively) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)

  • Page 28

    See Table 5-9: “Host Bus Interface Pin Mapping,” on page 31. This input pin is used to select between the memory and register address spaces of the S1D13504. M/R# is set high to access the memory and low to access the registers. See Section 8.1,...

  • Page 29

    Epson Research and Development Page 23 Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin # Reset = Pin Name Type Driver Description F00A 0 Value F02A F01A This pin has multiple functions. • For SH-3 mode, this pin inputs the write enable signal for the lower data byte (WE0#).

  • Page 30: Memory Interface

    Page 24 Epson Research and Development Vancouver Design Center 5.4.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions. • For dual CAS# DRAM, this is the column address strobe for the lower byte (LCAS#).

  • Page 31

    Epson Research and Development Page 25 Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A 43, 41, 46, 44, 39, 37, 42, 40, MA[8:0] 35, 34,...

  • Page 32: Lcd Interface

    Page 26 Epson Research and Development Vancouver Design Center 5.4.3 LCD Interface Table 5-3: LCD Interface Pin Descriptions Pin # Reset = Pin Name Type Driver Description F00A 0 Value F02A FPDAT[8:0] 88, 82-75 98, 92-85 CN3 Output 0 Panel Data These pins have multiple functions.

  • Page 33: Crt And External Ramdac Interface

    Epson Research and Development Page 27 Vancouver Design Center 5.4.5 CRT and External RAMDAC Interface Table 5-5: CRT and RAMDAC Interface Pin Descriptions Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions.

  • Page 34

    Page 28 Epson Research and Development Vancouver Design Center Table 5-5: CRT and RAMDAC Interface Pin Descriptions (Continued) Pin # Reset = 0 Pin Name Type Driver Description F00A Value F02A F01A This pin has multiple functions. • Horizontal Retrace signal for CRT.

  • Page 35: Miscellaneous

    This pin has multiple functions. • When MD9 = 0 at rising edge of RESET#, this pin is an active-low input used to place the S1D13504 into suspend mode; see Section 13, “Power Save Modes” on page 127 for details.

  • Page 36: Summary Of Configuration Options

    Page 30 Epson Research and Development Vancouver Design Center 5.5 Summary of Configuration Options Table 5-8: Summary of Power On / Reset Options value on this pin at rising edge of RESET# is used to configure: (1/0) Pin Name 8-bit host bus interface...

  • Page 37: Multiple Function Pin Mapping

    Epson Research and Development Page 31 Vancouver Design Center 5.6 Multiple Function Pin Mapping Table 5-9: Host Bus Interface Pin Mapping S1D13504 SH-3 MC68K Bus 1 MC68K Bus 2 Generic MPU Pin Names AB[20:1] A[20:1] A[20:1] A[20:1] A[20:1] LDS# DB[15:0]...

  • Page 38

    Page 32 Epson Research and Development Vancouver Design Center Table 5-10: Memory Interface Pin Mapping FPM/EDO-DRAM S1D13504 Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 Pin Names 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# 2-CAS# 2-WE# MD[15:0] DQ[15:0] MA[8:0] A[8:0] GPIO3...

  • Page 39

    Epson Research and Development Page 33 Vancouver Design Center Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping Monochrome Passive Color Passive Panel Panel Color TFT Panel S1D13504 Single Single Pin Names Single Dual Single Dual Format 1 Format 2 4-bit...

  • Page 40: D.c. Characteristics

    Page 34 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core V Supply Voltage - 0.3 to 4.6 IO V Supply Voltage - 0.3 to 6.0 Input Voltage - 0.3 to IO V + 0.5...

  • Page 41

    Epson Research and Development Page 35 Vancouver Design Center Table 6-4: Output Specifications Symbol Parameter Condition Units Low Level Output Voltage Type 1 - TS1, CO1, TS1D = 3mA Type 2 - TS2, CO2 = 6mA Type 3 - TS3, CO3...

  • Page 42: A.c. Characteristics

    CSn# WEn# WAIT# D[15:0](write) D[15:0](read) Figure 7-1: SH-3 Interface Timing Note The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value. S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 43

    Rising edge RD# to D[15:0] tri-state (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the fall- ing edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later.

  • Page 44: Mc68k Bus 1 Interface Timing (e.g. Mc68000)

    Page 38 Epson Research and Development Vancouver Design Center 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) A[20:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) Figure 7-2: MC68K Bus 1 Interface Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 45

    AS# or the first positive edge of CLK after A[20:1] and M/R# become val- whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become val- id, whichever occurs later.

  • Page 46: Mc68k Bus 2 Interface Timing (e.g. Mc68030)

    Page 40 Epson Research and Development Vancouver Design Center 7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030) A[20:0] SIZ[1:0] M/R# R/W# DSACK1# D[31:16](write) D[31:16](read) Figure 7-3: MC68K Bus 2 Interface Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 47

    AS# or the first positive edge of CLK after A[20:0] and M/R# become valid, whichever occurs later. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later.

  • Page 48: Generic Mpu Interface Synchronous Timing

    Page 42 Epson Research and Development Vancouver Design Center 7.1.4 Generic MPU Interface Synchronous Timing BCLK BCLK A[20:0] Valid M/R# RD0#,RD1# WE0#,WE1# Hi-Z Hi-Z WAIT# Hi-Z Hi-Z Valid D[15:0](write) Hi-Z Hi-Z Valid D[15:0](read) Figure 7-4: Generic MPU Interface Synchronous Timing...

  • Page 49

    RD0#, RD1# high to D[15:0] high impedance (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.

  • Page 50: Generic Mpu Interface Asynchronous Timing

    Page 44 Epson Research and Development Vancouver Design Center 7.1.5 Generic MPU Interface Asynchronous Timing BCLK BCLK A[20:0] Valid M/R# RD0#,RD1# WE0#,WE1# Hi-Z Hi-Z WAIT# Hi-Z Hi-Z Valid D[15:0](write) Hi-Z Hi-Z D[15:0](read) Valid Figure 7-5: Generic MPU Interface Asynchronous Timing...

  • Page 51

    RD0#, RD1# high to D[15:0] high impedance (read cycle) If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.

  • Page 52: Clock Input Requirements

    Page 46 Epson Research and Development Vancouver Design Center 7.2 Clock Input Requirements Clock Input Waveform V IL CLKI Figure 7-6: Clock Input Requirements Table 7-6: Clock Input Requirements Symbol Parameter Units Input Clock Period (CLKI) 12.5 CLKI Pixel Clock Period (PCLK) not shown...

  • Page 53

    Epson Research and Development Page 47 Vancouver Design Center Table 7-7: EDO DRAM Read Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 54: Edo-dram Write Timing

    Page 48 Epson Research and Development Vancouver Design Center 7.3.2 EDO-DRAM Write Timing Memory Clock RAS# CAS# MD(Write) Figure 7-8: EDO-DRAM Write Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 55

    Epson Research and Development Page 49 Vancouver Design Center Table 7-8: EDO DRAM Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 56: Edo-dram Read-write Timing

    Page 50 Epson Research and Development Vancouver Design Center 7.3.3 EDO-DRAM Read-Write Timing Memory Clock RAS# CAS# MD(Read) MD(Write) Figure 7-9: EDO-DRAM Read-Write Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 57

    Epson Research and Development Page 51 Vancouver Design Center Table 7-9: EDO DRAM Read-Write Timing Symbol Parameter Units Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 58: Edo-dram Cas Before Ras Refresh Timing

    Page 52 Epson Research and Development Vancouver Design Center 7.3.4 EDO-DRAM CAS Before RAS Refresh Timing Memory Clock RAS# CAS# Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing Symbol Parameter Units Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1...

  • Page 59: Edo-dram Self-refresh Timing

    Epson Research and Development Page 53 Vancouver Design Center 7.3.5 EDO-DRAM Self-Refresh Timing Restarted for Stopped for active mode suspend mode Memory Clock RAS# CAS# Figure 7-11: EDO-DRAM Self-Refresh Timing Table 7-11: EDO-DRAM Self-Refresh Timing Symbol Parameter Units Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1...

  • Page 60: Fpm-dram Read Timing

    Page 54 Epson Research and Development Vancouver Design Center 7.3.6 FPM-DRAM Read Timing Memory Clock RAS# CAS# MD(Read) Figure 7-12: FPM-DRAM Read Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 61

    Epson Research and Development Page 55 Vancouver Design Center Table 7-12: FPM DRAM Read Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 62: Fpm-dram Write Timing

    Page 56 Epson Research and Development Vancouver Design Center 7.3.7 FPM-DRAM Write Timing Memory Clock RAS# CAS# MD(Write) Figure 7-13: FPM-DRAM Write Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 63

    Epson Research and Development Page 57 Vancouver Design Center Table 7-13: FPM-DRAM Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 64: Fpm-dram Read-write Timing

    Page 58 Epson Research and Development Vancouver Design Center 7.3.8 FPM-DRAM Read-Write Timing Memory Clock RAS# CAS# MD(Read) MD(Write) Figure 7-14: FPM-DRAM Read-Write Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 65

    Epson Research and Development Page 59 Vancouver Design Center Table 7-14: FPM-DRAM Read-Write Timing Symbol Parameter Units Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 Random read or write cycle time (REG[22h] bits [6:5] = 01)

  • Page 66: Fpm-dram Cas# Before Ras# Refresh Timing

    Page 60 Epson Research and Development Vancouver Design Center 7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing Memory Clock RAS# CAS# Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Symbol Parameter Units Memory clock...

  • Page 67: Fpm-dram Self-refresh Timing

    Epson Research and Development Page 61 Vancouver Design Center 7.3.10 FPM-DRAM Self-Refresh Timing Restarted for Stopped for active mode suspend mode Memory Clock RAS# CAS# Figure 7-16: FPM-DRAM CBR Self-Refresh Timing Table 7-16: FPM-DRAM CBR Self-Refresh Timing Symbol Parameter Units...

  • Page 68: Display Interface

    Page 62 Epson Research and Development Vancouver Design Center 7.4 Display Interface 7.4.1 Power-On/Reset Timing RESET# RESET# LCD ENABLE (REG[0Dh] bit 0) Inactive Active LCDPWR Active FPFRAME FPLINE Active FPSHIFT FPDAT[15:0] DRDY Figure 7-17: LCD Panel Power-On/Reset Timing Table 7-17: LCD Panel Power-On/Reset Timing...

  • Page 69: Suspend Timing

    Epson Research and Development Page 63 Vancouver Design Center 7.4.2 Suspend Timing SUSPEND# Software Suspend Note 1 Note 2 CLKI LCDPWR Inactive Active Active FPFRAME FPLINE Active Active Inactive DRDY FPSHIFT Active Active FPDAT[15:0] Memory Access Allowed Allowed Not Allowed...

  • Page 70: Single Monochrome 4-bit Panel Timing

    Page 64 Epson Research and Development Vancouver Design Center 7.4.3 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-317 1-318 1-319 1-320 * Diagram drawn with 2 FPLINE vertical blank period...

  • Page 71

    Epson Research and Development Page 65 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing Symbol Parameter Units note 2 FPFRAME setup to FPLINE falling edge...

  • Page 72: Single Monochrome 8-bit Panel Timing

    Page 66 Epson Research and Development Vancouver Design Center 7.4.4 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 UD[3:0], LD[3:0] FPLINE HNDP FPSHIFT 1-633 1-10 1-634 1-11 1-635 1-12 1-636 1-13 1-637...

  • Page 73

    Epson Research and Development Page 67 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units note 2...

  • Page 74: Single Color 4-bit Panel Timing

    Page 68 Epson Research and Development Vancouver Design Center 7.4.5 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-R1 1-G2 1-B3 1-B319 1-G1 1-B2 1-R4 1-R320 1-G320 1-B1...

  • Page 75

    Epson Research and Development Page 69 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] Figure 7-24: Single Color 4-Bit Panel A.C. Timing Table 7-21: Single Color 4-Bit Panel A.C. Timing Symbol Parameter Units note 2 FPFRAME setup to FPLINE falling edge...

  • Page 76

    Page 70 Epson Research and Development Vancouver Design Center 7.4.6 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT FPSHIFT2 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12...

  • Page 77

    Epson Research and Development Page 71 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 UD[3:0] LD[3:0] Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)

  • Page 78

    Page 72 Epson Research and Development Vancouver Design Center 7.4.7 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-R1 1-B3 1-G6 1-G638 1-B638 1-G1 1-R4...

  • Page 79

    Epson Research and Development Page 73 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol...

  • Page 80: Single Color 16-bit Panel Timing

    Page 74 Epson Research and Development Vancouver Design Center 7.4.8 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE UD[7:0], LD[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HNDP FPSHIFT 1-G6 1-B11 1-G635 1-R1 1-G12 1-G636 1-B1 1-R7 1-B7...

  • Page 81

    Epson Research and Development Page 75 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[7:0] LD[7:0] Figure 7-30: Single Color 16-Bit Panel A.C. Timing Table 7-24: Single Color 16-Bit Panel A.C. Timing Symbol Parameter Units note 2...

  • Page 82: Dual Monochrome 8-bit Panel Timing

    Page 76 Epson Research and Development Vancouver Design Center 7.4.9 Dual Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE HNDP FPSHIFT 1-637...

  • Page 83

    Epson Research and Development Page 77 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units FPFRAME setup to FPLINE falling edge...

  • Page 84: Dual Color 8-bit Panel Timing

    Page 78 Epson Research and Development Vancouver Design Center 7.4.10 Dual Color 8-Bit Panel Timing VNDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241 FPLINE HNDP FPSHIFT 1-R1 1-G2 1-B 3 1-R 5 1-G6...

  • Page 85

    Epson Research and Development Page 79 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[3:0] LD[3:0] Figure 7-34: Dual Color 8-Bit Panel A.C. Timing Table 7-26: Dual Color 8-Bit Panel A.C. Timing Symbol Parameter Units note 2...

  • Page 86: Dual Color 16-bit Panel Timing

    Page 80 Epson Research and Development Vancouver Design Center 7.4.11 Dual Color 16-Bit Panel Timing VNDP FPFRAME FPLINE UD[7:0], LD[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE HNDP FPSHIFT UD7, LD7...

  • Page 87

    Epson Research and Development Page 81 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT UD[7:0] LD[7:0] Figure 7-36: Dual Color 16-Bit Panel A.C. Timing Table 7-27: Dual Color 16-Bit Panel A.C. Timing Symbol Parameter Units note 2...

  • Page 88: Bit Tft Panel Timing

    Page 82 Epson Research and Development Vancouver Design Center 7.4.12 16-Bit TFT Panel Timing VNDP FPFRAME FPLINE LINE480 LINE1 LINE480 R[5:1], G[5:0], B[5:1] DRDY FPLINE HNDP HNDP FPSHIFT DRDY R[5:1] 1-640 G [5:0] 1-640 B[5:1] 1-640 Note: DRDY is used to indicate the first pixel...

  • Page 89

    Epson Research and Development Page 83 Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Figure 7-38: TFT A.C. Timing Hardware Functional Specification S1D13504 Issue Date: 01/11/06 X19A-A-002-19...

  • Page 90

    Page 84 Epson Research and Development Vancouver Design Center Table 7-28: TFT A.C. Timing Symbol Parameter Units Ts (note 1) FPSHIFT period 0.45 FPSHIFT pulse width high 0.45 FPSHIFT pulse width low 0.45 data setup to FPSHIFT falling edge 0.45...

  • Page 91: Crt Timing

    Epson Research and Development Page 85 Vancouver Design Center 7.4.13 CRT Timing Example Timing for 640x480 CRT VNDP VRTC HRTC LINE480 LINE480 DACP[7:0] LINE1 BLANK# HRTC HNDP HNDP DACCLK BLANK# DACD[7:0] 1-640 Figure 7-39: CRT Timing = Vertical Display Period...

  • Page 92

    Page 86 Epson Research and Development Vancouver Design Center VRTC HRTC HRTC BLANK# DACCLK DACD[7:0] Figure 7-40: CRT A.C. Timing S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 93

    Epson Research and Development Page 87 Vancouver Design Center Table 7-29: CRT A.C. Timing Symbol Parameter Units Ts (note 1) DACCLK period 0.45 DACCLK pulse width high 0.45 DACCLK pulse width low 0.45 data setup to DACCLK rising edge 0.45...

  • Page 94: External Ramdac Read / Write Timing

    Page 88 Epson Research and Development Vancouver Design Center 7.4.14 External RAMDAC Read / Write Timing Read AB[20:0] M/R# DACRS[1:0] Valid RD# Command (depends on CPU bus) DACRD# Write Valid WR# command (depends on CPU bus) DACWR# Figure 7-41: Generic Bus RAMDAC Read / Write Timing...

  • Page 95: Registers

    8 Registers 8.1 Register Mapping The S1D13504 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.

  • Page 96: Memory Configuration Registers

    This bit should be changed only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

  • Page 97: Panel/monitor Configuration Registers

    Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle. The Half Frame Buffer is idle during vertical non-display periods or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

  • Page 98

    Page 92 Epson Research and Development Vancouver Design Center Horizontal Display Width Register REG[04h] Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4...

  • Page 99

    Epson Research and Development Page 93 Vancouver Design Center HRTC/FPLINE Pulse Width Register REG[07h] HRTC FPLINE HRTC/ HRTC/ HRTC/ HRTC/ Polarity Polarity FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Select Select Width Bit 3 Width Bit 2 Width Bit 1...

  • Page 100

    Page 94 Epson Research and Development Vancouver Design Center Vertical Non-Display Period Register REG[0Ah] Vertical Vertical Vertical Vertical Vertical Vertical Vertical Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Non-Display Period Status Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2...

  • Page 101

    Epson Research and Development Page 95 Vancouver Design Center VRTC/FPFRAME Pulse Width Register REG[0Ch] VRTC/ VRTC/ VRTC/ FPFRAME VRTC Polarity FPFRAME FPFRAME FPFRAME Polarity Select Pulse Width Pulse Width Pulse Width Select Bit 2 Bit 1 Bit 0 bit 7 VRTC Polarity Select For CRTs, this bit selects the polarity of the VRTC.

  • Page 102: Display Configuration Registers

    Page 96 Epson Research and Development Vancouver Design Center 8.2.4 Display Configuration Registers Display Mode Register REG[0Dh] Simultaneous Simultaneous Number Of Number Of Number Of Display Display Bits/Pixel Bits/Pixel Bits/Pixel CRT Enable LCD Enable Option Select Option Select Select Bit 2...

  • Page 103

    Epson Research and Development Page 97 Vancouver Design Center bits 4-2 Number of Bits-Per-Pixel Select Bits [2:0] These bits select the number of bits-per-pixel (bpp) for the displayed data. Note 15 and 16-bpp modes bypass the LUT and are supported as 12-bpp on passive panels and 15/16- bpp on TFT panels.

  • Page 104

    Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 2, if (ContentsOfThisRegister) > 00EFh Note For further details, see Section 10.2, “Image Manipulation” on page 117 and the S1D13504 Pro- gramming Notes and Examples, document number X19A-G-002-xx. S1D13504...

  • Page 105

    Epson Research and Development Page 99 Vancouver Design Center Screen 1 Display Start Address Register 0 REG[10h] Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4...

  • Page 106

    15/16 Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register. See Section 10, “Display Configuration” on page 115 and S1D13504 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.

  • Page 107: Clock Configuration Register

    Epson Research and Development Page 101 Vancouver Design Center 8.2.5 Clock Configuration Register Clock Configuration Register REG[19h] MCLK Divide PCLK Divide PCLK Divide Select Select Bit 1 Select Bit 0 bit 2 MCLK Divide Select When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When this bit = 0 the memory clock frequency is equal to the input clock frequency.

  • Page 108: Miscellaneous Registers

    The Half Frame Buffer should be disabled only when idle. The Half Frame Buffer is idle during vertical non-display periods (i.e. when REG[0Ah] bit 7 = 1), or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

  • Page 109

    Epson Research and Development Page 103 Vancouver Design Center GPIO Configuration Register 0 REG[1Eh] GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Pin IO Config. IO Config. IO Config. IO Config. IO Config.

  • Page 110

    Page 104 Epson Research and Development Vancouver Design Center GPIO Configuration Register 1 REG[1Fh] GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config. IO Config. IO Config. IO Config. bit 3 GPIO11 Pin IO Configuration When this bit = 1, GPIO11 is configured as an output. When this bit = 0 (default), GPIO11 is con- figured as an input.

  • Page 111

    Epson Research and Development Page 105 Vancouver Design Center GPIO Status / Control Register 0 REG[20h] GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Pin IO Status IO Status IO Status IO Status...

  • Page 112

    LCD backlight power: • When MD9 = 0 at rising edge of RESET#, SUSPEND# is an active-low Schmitt input used to put the S1D13504 into suspend mode - see Section 13, “Power Save Modes” on page 127 for details.

  • Page 113

    DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

  • Page 114

    Page 108 Epson Research and Development Vancouver Design Center bit 4 RAS# to CAS# Delay (N This bit selects the DRAM RAS# to CAS# delay parameter, t . This bit specifies the number ) of MCLK periods (T ) used to create t...

  • Page 115

    When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen is blanked). This allows the S1D13504 to be dedicated to service CPU to memory accesses. When this bit = 0 the display FIFO is enabled.

  • Page 116: Look-up Table Registers

    Vancouver Design Center 8.2.8 Look-Up Table Registers The S1D13504 has three internal 16 position, 4-bit wide Look-Up Tables. The 4-bit value programmed into each table position determines the color weighting of display data; the output gray shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode.

  • Page 117: External Ramdac Control Registers

    Epson Research and Development Page 111 Vancouver Design Center Look-Up Table Bank Select Register REG[27h] Red Bank Red Bank Blue Bank Blue Bank Green Bank Green Bank Select Bit 1 Select Bit 0 Select Bit 1 Select Bit 0 Select Bit 1...

  • Page 118

    Page 112 Epson Research and Development Vancouver Design Center RAMDAC Read Mode Address Register REG[2Ah] or REG[2Bh] RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC RAMDAC Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3...

  • Page 119: Display Buffer

    The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table. Table 9-1: S1D13504 Addressing M/R# Access Register access: •...

  • Page 120: Image Buffer

    Page 114 Epson Research and Development Vancouver Design Center 9.1 Image Buffer The image buffer contains the formatted display data - see Section 10.1, “Display Mode Data Format” on page 115. The displayed image(s) may take up only a portion of the image buffer; the remaining area can be used for multiple images - possibly for animation or general storage.

  • Page 121: Display Configuration

    Epson Research and Development Page 115 Vancouver Design Center 10 Display Configuration 10.1 Display Mode Data Format 1-bpp: bit 7 bit 0 Byte 0 = (A Panel Display Host Address Display Buffer 2-bpp: bit 7 bit 0 Byte 0 Byte 1...

  • Page 122

    Page 116 Epson Research and Development Vancouver Design Center 15-bpp: 5-5-5 RGB bit 7 bit 0 Byte 0 = (R Byte 1 Passive = (R Byte 2 Panel Display Byte 3 Display Buffer Host Address 16-bpp: 5-6-5 RGB bit 7...

  • Page 123: Image Manipulation

    Epson Research and Development Page 117 Vancouver Design Center 10.2 Image Manipulation The figure below shows how screen 1 and screen 2 images stored in the image buffer are positioned on the display. The screen 1 and screen 2 images can be parts of a larger virtual image or images.

  • Page 124: Clocking

    Page 118 Epson Research and Development Vancouver Design Center 11 Clocking 11.1 Maximum MCLK: PCLK Ratios Table 11-1: Maximum PCLK Frequency with EDO-DRAM Maximum PCLK Allowed Display type 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp • Single Panel.

  • Page 125: Frame Rate Calculation

    Epson Research and Development Page 119 Vancouver Design Center 11.2 Frame Rate Calculation The frame rate is calculated using the following formula: PCLK FrameRate ---------------------------------------------------------------------------------------- - × HNDP VNDP Where: = Vertical Display Period = REG[09h] bits [1:0], REG[08h] bits [7:0] + 1...

  • Page 126

    Page 120 Epson Research and Development Vancouver Design Center Table 11-3: Example Frame Rates Maximum Maximum Frame Color Minimum DRAM Type Pixel Rate (Hz) Display Resolution Depth Panel (Speed Grade) Clock (bpp) HNDP(T Panel (MHz) • Single Panel. 1/2/4/8 800x600 •...

  • Page 127: Look-up Table Architecture

    Epson Research and Development Page 121 Vancouver Design Center 12 Look-Up Table Architecture Table 12-1: Look-Up Table Configurations Display Mode 4-Bit Wide Look-Up Table GREEN BLUE Black & White 1 bank of 2 entries 4-level gray 4 banks of 4 entries...

  • Page 128

    Page 122 Epson Research and Development Vancouver Design Center 2 Bit-Per-Pixel Mode Green Look-Up Table Bank 0 Bank 1 Selected Bank Entry Bank 4-bit display data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0] REG[27h] bits [1:0] 2-bit pixel data Note: the above depiction is intended to show the display data output path only.

  • Page 129: Color Display Modes

    Epson Research and Development Page 123 Vancouver Design Center 12.2 Color Display Modes 1 Bit-Per-Pixel Color Mode Red Look-Up Table Entry 4-bit Red data output Select Logic 1-bit pixel data Green Look-Up Table Entry 4-bit Green data output Select Logic...

  • Page 130

    Page 124 Epson Research and Development Vancouver Design Center 2 Bit-Per-Pixel Color Mode Red Look-Up Table Bank 0 Bank 1 Selected Bank Entry Bank 4-bit Red data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0]...

  • Page 131

    Epson Research and Development Page 125 Vancouver Design Center 4 Bit-Per-Pixel Color Mode Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110 4-bit Red data output 0111 Select 1000 Logic 1001 1010 1011 1100 1101 1110 1111 4-bit pixel data...

  • Page 132

    Page 126 Epson Research and Development Vancouver Design Center 8 Bit-Per-Pixel Color Mode 256 Color Data Format: Red Look-Up Table Bank 0 R2 R1 R0 G2 G1 G0 B1 B0 Selected Bank Entry Bank 4-bit Red data output Select Bank 1...

  • Page 133: Power Save Modes

    Page 127 Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13504 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend.

  • Page 134: Power Save Mode Function Summary

    Page 128 Epson Research and Development Vancouver Design Center 13.3 Power Save Mode Function Summary Table 13-1: Power Save Mode Function Summary Power Save Mode (PSM) Function Normal Software Hardware (Active) Suspend Suspend Display Active? Register Access Possible? Yes (1)

  • Page 135: Mechanical Data

    Epson Research and Development Page 129 Vancouver Design Center 14 Mechanical Data 14.1 QFP15-128 (S1D13504F00A) QFP15 - 128 pin Unit: mm 16.0 ± 0.4 14.0 ± 0.1 Index 0.16 ± 0.1 0~10° 0.5 ± 0.2 Figure 14-1: Mechanical Drawing QFP15-128...

  • Page 136: Tqfp15-128 (s1d13504f01a)

    Page 130 Epson Research and Development Vancouver Design Center 14.2 TQFP15-128 (S1D13504F01A) TQFP15 - 128 pin Unit: mm ±0.4 ±0.1 INDEX +0.05 0.16 - 0.03 +0.05 0.125 - 0.025 0 ° 10 ° ±0.2 Figure 14-2: Mechanical Drawing TQFP15-128 S1D13504...

  • Page 137: Qfp20-144 (s1d13504f02a)

    Epson Research and Development Page 131 Vancouver Design Center 14.3 QFP20-144 (S1D13504F02A) QFP20 - 144 pin Unit: mm ±0.4 ±0.1 INDEX +0.1 - 0.05 +0.05 0.125 - 0.025 0 ° 10 ° ±0.2 Figure 14-3: Mechanical Drawing QFP20-144 Hardware Functional Specification...

  • Page 138: References

    Epson Research and Development Vancouver Design Center 15 References The following documents contain additional information related to the S1D13504. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com.

  • Page 139: Sales And Technical Support

    Epson Research and Development Page 133 Vancouver Design Center 16 Sales and Technical Support Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd. 421-8, Hino, Hino-shi San Jose, CA 95134, USA 10F, No.

  • Page 140

    Page 134 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Hardware Functional Specification X19A-A-002-19 Issue Date: 01/11/06...

  • Page 141

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 142

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...

  • Page 143

    Introduction ..........7 Programming the S1D13504 Registers ......8 Registers Requiring Special Consideration .

  • Page 144

    Identifying the S1D13504 ........

  • Page 145

    Table 2-1: Initializing the S1D13504 Registers ....... . . 10 Table 3-1: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer .

  • Page 146

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...

  • Page 147

    Vancouver Design Center 1 Introduction This guide describes how to program the S1D13504 Color Graphics LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13504.

  • Page 148

    This section describes how to program the S1D13504 registers that require special consideration. It also provides the correct sequence for initializing the S1D13504 and disabling the half frame buffer. For further information on the any of the registers described below, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

  • Page 149

    2.2 Register Initialization 2.2.1 Initialization Sequence To initialize the S1D13504 after POWER-ON or a HARDWARE RESET, do the following: Enable the host interface (REG[1Bh] bit 7=0). Disable the display FIFO (REG[23h] bit 7=1) after stopping FIFO accesses to the DRAM.

  • Page 150

    Example 1: Initialize the registers for a 16 color 640x480 dual passive LCD using a 16 bit data interface; assume 2M byte of display buffer. Program the S1D13504 registers in the following order with the data supplied. Note that for this example, it is assumed that the arrays “unsigned char RED[16], GREEN[16], BLUE[16]” are defined and initialized for the required colors.

  • Page 151

    Epson Research and Development Page 11 Vancouver Design Center Table 2-1: Initializing the S1D13504 Registers (Continued) REG[20h] = 0x00 General I/O Control REG[21h] = 0x00 REG[24h] = 0x00 Look-Up Table Address for (index = 0; index < 16; ++index) { Update Look-Up Table based on the REG[26h] = RED[index];...

  • Page 152

    3.1 Display Buffer Location The S1D13504 requires either a 512K byte or a 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block; the S5U13504B00C evalu- ation board decodes the display buffer at the 12M byte location of system memory.

  • Page 153

    Epson Research and Development Page 13 Vancouver Design Center 3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades) Two pixels are grouped into one byte of display buffer as shown below: Table 3-3: Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer...

  • Page 154

    Page 14 Epson Research and Development Vancouver Design Center 3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors) One pixel is stored in two bytes of display buffer as shown below: Table 3-5: Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer...

  • Page 155

    Select Bit 1 Select Bit 0 The S1D13504 LUT Registers are located at offsets 24h, 26h and 27h. They consist of a LUT address register, data register and bank register. Refer to the S1D13504 Hardware Functional Speci- fication document number X19A-A-002-xx for more details.

  • Page 156

    Page 16 Epson Research and Development Vancouver Design Center Bank Select Bits LUT banks are provided to give the application developer a choice of colors/gray shades. While the chosen color depth (bpp) may limit the simultaneous colors available, the panel is capable of storing different combinations of colors in banks.

  • Page 157

    0 and 0Fh. • The S1D13504 LUT is linear; increasing the LUT number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red Look-Up entry will always result in a bright red output.

  • Page 158

    Vancouver Design Center Color Modes In color mode, the S1D13504 supports three, 16 position, 4 bit wide color LUTs (red, green, and blue). Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks. 1 bpp Color In 1 bpp color mode, the LUT is limited to a single 2 entry bank per color.

  • Page 159

    Epson Research and Development Page 19 Vancouver Design Center 4 bpp Color In 4 bpp color mode, the LUT is limited to a single 16 entry bank per color. The LUT bank select bits have no effect in this mode.

  • Page 160

    =4096 colors. Gray Shade Modes In gray shade mode, the S1D13504 treats the Green LUT as a 16 position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from 1 to 4 banks. 1 bpp Gray Shade The S1D13504 has no true Black-and-White mode.

  • Page 161

    8 bpp Gray Shade When the S1D13504 is configured for 8 bpp gray shade mode, bits [7:5] are ignored, bits [4:2] represent the green LUT index, and bits [1:0] are ignored. Only 3 bits of the 8 that actually represent any shade value, therefore the maximum gray shade combination is 8 shades.

  • Page 162

    Page 22 Epson Research and Development Vancouver Design Center 15 bpp Gray Shade Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data.

  • Page 163

    The size of the virtual display is limited by the amount of available display buffer. In the case of an S1D13504 with 2M byte of display buffer, the maximum virtual width ranges from 16,368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode. The maximum vertical size at the horizontal maximum is 1025 lines.

  • Page 164

    “virtual” image. After determining the amount of memory used by each line, do a calculation to see if there is enough memory to support the desired number of lines. Initialize the S1D13504 registers for a 320x240 panel. (See Section 2.2, “Register Initialization” on page 9).

  • Page 165

    Update the pixel paning register. Note The S1D13504 provides a false indication of vertical non-display period when used with a dual panel display. In this case it is impossible to identify the false signal from the true non-display period. The result is that panning operations at less than 15 bpp may exhibit an occasional tear as the result of updating registers in the wrong order.

  • Page 166

    Page 26 Epson Research and Development Vancouver Design Center 4.2.1 Registers REG[10h] Screen 1 Display Start Address 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5...

  • Page 167

    Epson Research and Development Page 27 Vancouver Design Center 4.2.2 Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport. Refer to Section 2.2, “Register Initialization” on page 9 and Section 4.1, “Virtual Display”...

  • Page 168

    The Split Screen feature of the S1D13504 allows a programmer to set up a display for such an appli- cation. The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239.

  • Page 169

    Epson Research and Development Page 29 Vancouver Design Center REG[13h] Screen 2 Display Start Address Register 0 Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4...

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    The S1D13504 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down. Conversely, the LCD signals must be active prior to the power supply starting up.

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    LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage. Controlling the LCD Drive Power Supply can be done using the S1D13504 LCDPWR# output signal or by 'other' means. The following example assumes that the LCDPWR# pin is being used.

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    Page 32 Epson Research and Development Vancouver Design Center 3. Enable Hardware Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced. 4. Disable Hardware Suspend. 5. Restore the Horzontal and Vertical resolution registers to their original values.

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    6 CRT Considerations 6.1 Introduction The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Frame Rate Calculation (Chapter 11)” in S1D13504 Hardware Functional Specification. The following sections describe CRT considerations. 6.1.1 CRT Only For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel.

  • Page 174

    40 MHz and 85 Hz respectively. When pixel depth is less than 8 bpp, the RAMDAC is programmed with the same values as the Look-Up Table. The S1D13504 does not support Simulta- neous Display in a color depth greater than 8 bpp.

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    Epson Research and Development Page 35 Vancouver Design Center Table 6-3: 8 bpp Recommended RAMDAC palette data for Simultaneous Display Address Address Address Address Programming Notes and Examples S1D13504 Issue Date: 01/02/01 X19A-G-002-07...

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    Page 36 Epson Research and Development Vancouver Design Center Address Address Address Address S1D13504 Programming Notes and Examples X19A-G-002-07 Issue Date: 01/02/01...

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    Epson Research and Development Page 37 Vancouver Design Center Table 6-4: Related register data for Simultaneous Display 640X480@75Hz 640X480@60Hz Register Notes PCLK=40.0MHz PCLK=40.0MHz REG[04h] set horizontal display width 0100 1111 0100 1111 REG[05h] set horizontal non-display period 0001 1101 0001 0011...

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    Vancouver Design Center 7 Identifying the S1D13504 Unlike previous generations of S1D1350x products, the S1D13504 can be identified at any time after power-on/reset. The S1D13504 and future S1D1350x products can be identified by reading REG[00h]. The value of this register for the S1D13504F00A is 04h.

  • Page 179

    The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and configure the S1D13504. HAL allows easy porting from one S1D1350x product to another and between system architectures. HAL is included in the utilities provided with the S1D13504 evaluation system.

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    Page 40 Epson Research and Development Vancouver Design Center int seGetId(int device, BYTE *pId) Description: Reads the revision code register to determine the ID. Parameter: device - registered device ID pId - pointer to allocated byte. The following are the possible values set to *pId:...

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    Epson Research and Development Page 41 Vancouver Design Center int seSetInit(int device) Description: Sets the system to an operational state by initializing memory size, clocks, panel and CRT parameters,... etc. Parameter: device - registered device ID Return Value: ERR_OK - operation completed with no problems...

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    Page 42 Epson Research and Development Vancouver Design Center int seGetBitsPerPixel(int device, BYTE *pBitsPerPixel) Description: Determines the color depth of current display mode. Parameter: device - registered device ID pBitsPerPixel - if ERR_OK, *pBitsPerPixel set Return Value: ERR_OK - operation completed with no problems...

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    Epson Research and Development Page 43 Vancouver Design Center int seGetScreenSize(int device, int *width, int *height) Description: Determines the width and height of the active display device (LCD or CRT). Parameter: device - registered device ID width - width of display in pixels height - height of display in pixels Return Value: ERR_OK - operation completed with no problems.

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    Page 44 Epson Research and Development Vancouver Design Center int seSetBitsPerPixel(int device, BYTE BitsPerPixel) Description: Sets the number of bpp. This function is equivalent to a mode set. Parameter: device - registered device ID BitsPerPixel - desired number of bpp Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.

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    Epson Research and Development Page 45 Vancouver Design Center int seVirtInit(int device, int xVirt, long *yVirt) Description: Creates a virtual display with the given horizontal size and determines the maximum number of available lines. Parameter: device - registered device ID xVirt - horizontal size of virtual display in pixels.

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    Page 46 Epson Research and Development Vancouver Design Center int seWriteDisplayBytes(int device, DWORD addr, BYTE val, DWORD count) Description: Writes one or more bytes to the display buffer. Parameter: device - registered device ID addr - offset from start of the display buffer...

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    Epson Research and Development Page 47 Vancouver Design Center 8.2.3 Color Manipulation int seGetDac(int device, BYTE *pDac) Description: Reads the entire DAC into an array. Parameter: device - registered device ID pDac - pointer to an array of BYTE dac[256][3]...

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    Page 48 Epson Research and Development Vancouver Design Center int seGetLutEntry(int device, BYTE index, BYTE *pEntry); Description: Reads one LUT entry. Parameter: device - registered device ID index - index to LUT entry (0 to 15) pEntry - pointer to an array of BYTE entry[3]...

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    Epson Research and Development Page 49 Vancouver Design Center int seSetLut(int device, BYTE *pLut) Description: Writes the entire LUT from an array into the LUT registers. Parameter: device - registered device ID pLut - pointer to an array of BYTE lut[16][3]...

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    Page 50 Epson Research and Development Vancouver Design Center 8.2.4 Drawing int seDrawLine(int device, int x1, int y1, int x2, int y2, DWORD color) Description: Draws a line on the display. Parameter: device - registered device ID. (x1, y1) - top left corner of line...

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    Epson Research and Development Page 51 Vancouver Design Center int seFillRect(int device, int x1, int y1, int x2, int y2, DWORD color) Description: Draws a solid rectangle on the display. Parameter: device - registered device ID (x1, y1) - top left corner of rectangle...

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    Page 52 Epson Research and Development Vancouver Design Center int seSetPixel(int device, int x, int y, DWORD color) Description: Writes a pixel to the display buffer. Parameter: device - Registered device ID x - horizontal coordinate of the pixel (starting from 0) y - vertical coordinate of the pixel (starting from 0) color - for 1,2,4,8 BPP: refers to index into LUT/DAC.

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    Epson Research and Development Page 53 Vancouver Design Center WORD seRotateByteLeft(BYTE val, BYTE bits) Description: Rotates the bits in “val” left as many times as stated in “bits”. Parameter: val - value to rotate bits - how many bits to rotate...

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    Vancouver Design Center 9 Sample Code 9.1 Introduction The following code samples demonstrate two approaches to initializing the S1D13504 color graphics controller with/without using the 13504HAL API. These code samples are for example purposes only. 9.1.1 Sample code using 13504HAL API **------------------------------------------------------------------------- Created 1998, Epson Research &...

  • Page 195

    0, 0xffffffff, 0x200000/4); exit(0); 9.1.2 Sample code without using 13504HAL API **=========================================================================== INIT13504.C - sample code demonstrating the initialization of the S1D13504. Beta release 2.0 98-10-22 The code in this example will perform initialization to the following specification: - 320 x 240 single 8-bit color passive panel.

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    0x06, 0x06, 0x0F, 0x09, 0x09, 0x00, 0x0B, 0x0B, 0x00, 0x0D, 0x0D, 0x00, 0x0F, 0x0F, 0x00, ** REGISTER_OFFSET points to the starting address of the S1D13504 registers #define REGISTER_OFFSET ((unsigned char *) 0x1234) void main(void) unsigned char * pRegs; unsigned char * pLUT;...

  • Page 197

    Epson Research and Development Page 57 Vancouver Design Center *(pRegs + 0x1B) = 0x00; /* 0000 0000 */ ** Step 2: Disable the display FIFO *(pRegs + 0x23) = 0x80; ** Step 3: Set the memory type ** Register 1: Memory Configuration - 4 ms refresh, EDO *(pRegs + 0x01) = 0x30;...

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    Page 58 Epson Research and Development Vancouver Design Center ** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only. *(pRegs + 0x06) = 0x00; /* 0000 0000 */ ** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.

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    Epson Research and Development Page 59 Vancouver Design Center ** Register 16-17: Memory Address Offset - this address represents the starting WORD. At 8BPP our 320 pixel width is 160 WORDS *(pRegs + 0x16) = 0xA0; /* 1010 0000 */ *(pRegs + 0x17) = 0x00;...

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    Page 60 Epson Research and Development Vancouver Design Center for (idx = 0; idx < 8; idx++) for (rgb = 0; rgb < 3; rgb++) *(pRegs + 0x26) = *pLUT; pLUT++; ** Registers 28-2E: RAMDAC - not used in this example. Programmed very similarly to the LUT but all 256 entries are used.

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    Epson Research and Development Page 61 Vancouver Design Center Appendix A Supported Panel Values A.1 Supported Panel Values The following tables show related register data for different panels. All the examples are based on 8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.

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    Page 62 Epson Research and Development Vancouver Design Center Table 9-3: TFT Panel TFT 16-Bit Single Register Notes 640X480@47Hz Color REG[02h] set panel type 0010 0101 REG[03h] set MOD rate 0000 0000 REG[04h] set horizontal display width 0100 1111 REG[05h]...

  • Page 205

    S1D13504 Color Graphics LCD/CRT Controller 13504CFG.EXE Configuration Program Document Number: X19A-B-001-04...

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    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. S1D13504 13504CFG.EXE Configuration Program...

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    Epson Research and Development Page 3 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...

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    Page 4 Epson Research and Development Vancouver Design Center Table of Contents 13504CFG.EXE ..........7 Program Requirements .

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    Epson Research and Development Page 5 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...

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    Page 6 Epson Research and Development Vancouver Design Center List of Figures Figure 1: 13504CFG Menu Bar ......... . 10 Figure 2: 13504CFG Open File .

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    Epson Research and Development Page 7 Vancouver Design Center THIS PAGE LEFT BLANK 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...

  • Page 212

    13504CFG gives a software/hardware developer an easy way to modify panel types, modes, etc. for the S1D13504 utilities without recompiling. Once the correct operating environment has been deter- mined, the software/hardware developer can modify the source code manually for a permanent change.

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    Epson Research and Development Page 9 Vancouver Design Center Program Requirements Video Controller : Any VGA Display Type : LCD or CRT BIOS : Any manufacturer’s VGA BIOS DOS Program : Yes DOS Version : 3.0 or greater Windows Program...

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    Page 10 Epson Research and Development Vancouver Design Center Script Mode In script mode, a file provides 13504CFG with all the information necessary to reconfigure the selected 13504 utility. Any changes which can be made by the interactive user interface can also be done by the script file.

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    Epson Research and Development Page 11 Vancouver Design Center Interactive Mode 13504CFG Menu Bar Menu Bar Figure 1: 13504CFG Menu Bar 13504CFG has four main menus: Files, View, Device, and Help. Menu contents can be viewed by using either the mouse or the keyboard.

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    Page 12 Epson Research and Development Vancouver Design Center Making 13504CFG Menu Selections In 13504CFG, a selection is made by clicking the left mouse button, or by pressing the tab and arrow keys on the keyboard. In the example below, there are three ways to select and open 13504SHOW.EXE in the Files box in the Open File window (figure 2).

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    Epson Research and Development Page 13 Vancouver Design Center Files Menu Figure 3: 13504CFG Files Menu The Files menu contains these functions: • Open - reads the HAL configuration for a given utility. Note A utility must be opened before any other menu command can be executed.

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    Notes and Examples” manual, document number X19A-G-002-xx for formulas and other infor- mation. Note Epson R&D Inc. cannot be held liable for damage done to the display as a result of software con- figuration errors. Cancel and Print commands are available in the Current/Advanced Configuration windows. Help is listed, but is not available for this version of 13504CFG.

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    Epson Research and Development Page 15 Vancouver Design Center Figure 5: 13504CFG Current Configuration Figure 6: 13504CFG Advanced Configuration (Partial View of Screen) 13504CFG.EXE Configuration Program S1D13504 Issue Date: 01/01/30 X19A-B-001-04...

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    Page 16 Epson Research and Development Vancouver Design Center Device Menu Figure 7: 13504CFG Device Menu The Device menu contains the following sub-menus where parameters for a S1D13504 utility can be edited: • Panel • CRT • Advanced Memory • Power Management •...

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    Epson Research and Development Page 17 Vancouver Design Center Panel Panel Setup When Panel is selected from the Device menu, the Panel Setup dialog box is displayed. To select a panel assignment, highlight it (in the example window below, “STN 4 Bit Mono Single 320x240”...

  • Page 222

    Page 18 Epson Research and Development Vancouver Design Center Edit Panel Setup When a selection is highlighted in the Panel Setup window and Edit is clicked, the Edit Panel Setup window is displayed. The Edit Panel Setup window lists parameters which can be edited, as shown below in Figure 9, “13504CFG Edit Panel Setup.”...

  • Page 223

    Epson Research and Development Page 19 Vancouver Design Center CRT Setup When CRT is selected from the Device menu, the CRT Setup window is displayed. To select a CRT assignment, highlight it (in the example window below, “CRT 640x400 @ 85Hz, CLKI=33.333MHz”...

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    Page 20 Epson Research and Development Vancouver Design Center Edit CRT Setup When a selection is highlighted in the CRT Setup window and Edit is clicked, the Edit CRT Setup window is displayed. The Edit CRT Setup window lists parameters which can be edited, as shown below in Figure 12, “13504CFG Edit CRT Setup.”...

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    Epson Research and Development Page 21 Vancouver Design Center Advanced Memory Memory Setup When Advanced Memory is selected from the Device menu, the Memory Setup dialog box is displayed. To select a memory assignment, highlight it ( in the example window below, “Memory Type 0”...

  • Page 226

    Page 22 Epson Research and Development Vancouver Design Center Edit Advanced Memory Setup When a selection is highlighted in the Memory Setup window and Edit is clicked, the Edit Advanced Memory Setup window is displayed. The Edit Advanced Memory window lists parameters which can be edited, as shown below in Figure 15, “13504CFG Edit Advanced Memory Setup.”...

  • Page 227

    Epson Research and Development Page 23 Vancouver Design Center Power Management Power Setup When Power Management is selected from the Device menu, the Power Setup dialog box is displayed. To select a power assignment, highlight it (in the example window below, “Power Type 0”...

  • Page 228

    Page 24 Epson Research and Development Vancouver Design Center Edit Power Setup When a selection is highlighted in the Power Setup window and Edit is clicked, the Edit Power Setup window is displayed. The Edit Power Setup window lists parameters which can be edited, as shown below in Figure 18, “13504CFG Edit Power Setup.”...

  • Page 229

    Epson Research and Development Page 25 Vancouver Design Center Lookup Table (LUT) LUT Setup When Lookup Table is selected from the Device menu, the LUT Setup dialog box is displayed. To select a LUT assignment, highlight it (in the example window below, “LUT Internal 4 Color” is highlighted) and click OK.

  • Page 230

    Page 26 Epson Research and Development Vancouver Design Center Edit LUT Setup When a selection is highlighted in the LUT Setup window and Edit is clicked, the Edit LUT Setup window is displayed. The Edit LUT Setup window lists parameters which can be edited, as shown below in Figure 21, “13504CFG Edit LUT Setup.”...

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    Epson Research and Development Page 27 Vancouver Design Center Setup When Setup is selected from the Device menu, the Setup dialog box is displayed. To select either Register Location, Memory Location, or Memory Size, highlight it (in the example window below, “Register Location: 00C00000 (hex)”...

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    Page 28 Epson Research and Development Vancouver Design Center Setup Parameter Edit When a selection is highlighted in the Setup window and Edit is clicked, a Setup Parameter Edit window is displayed for parameter editing. The Setup Parameter Edit windows for Register Location, Memory Location, and Memory Size respectively are shown below.

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    Vancouver Design Center Comments It is assumed that the 13504CFG user is familiar with S1D13504 hardware and software. Refer to the S1D13504 “Functional Hardware Specification,” document number X19A-A-002-xx, and the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx for information.

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    Page 30 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504CFG.EXE Configuration Program X19A-B-001-04 Issue Date: 01/01/30...

  • Page 235

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 236

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SHOW Demonstration Program X19A-B-002-05 Issue Date: 01/01/30...

  • Page 237

    • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504SHOW.EXE to a directory that is in the DOS path on your hard...

  • Page 238

    CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.

  • Page 239

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 240

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A-B-003-05 Issue Date: 01/01/30...

  • Page 241

    • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504SPLT.EXE to a directory that is in the DOS path on your hard...

  • Page 242

    Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504splt [/a]. Embedded platform: execute 13504splt and at the prompt, type the command line argument. Where: enables manual split screen operation no argument enables automatic split screen operation The following keyboard commands are for navigation within the program.

  • Page 243

    CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.

  • Page 244

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504SPLT Display Utility X19A-B-003-05 Issue Date: 01/01/30...

  • Page 245

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 246

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504VIRT Display Utility X19A-B-004-05 Issue Date: 01/01/30...

  • Page 247

    • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504VIRT.EXE to a directory that is in the DOS path on your hard...

  • Page 248

    Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504virt [/A] [/W=???]. Embedded platform: execute 13504virt and at the prompt, type the command line argument. Where: panning and scrolling is performed manually no argument...

  • Page 249

    CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.

  • Page 250

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504VIRT Display Utility X19A-B-004-05 Issue Date: 01/01/30...

  • Page 251

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 252

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PLAY Diagnostic Utility X19A-B-005-05 Issue Date: 01/02/01...

  • Page 253

    • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504PLAY.EXE to a directory that is in the DOS path on your hard...

  • Page 254

    Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504play [/?]. Embedded platform: execute 13504play and at the prompt, type the command line argument. Where: /? displays program revision information. The following commands are valid within the 13504PLAY program.

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    This causes the file “dumpregs.scr” to be interpreted and the results to be sent to the file “results.” Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the S1D13504 and reads the registers ; Note: after a semi-colon (;), all characters on a line are ignored...

  • Page 256

    CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. Program Messages ERROR: Too many devices registered.

  • Page 257

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 258

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504BMP Demonstration Program X19A-B-006-04 Issue Date: 01/02/01...

  • Page 259

    CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. 13504BMP Demonstration Program...

  • Page 260

    13504CFG configuration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. S1D13504...

  • Page 261

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 262

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A-B-007-04 Issue Date: 01/02/01...

  • Page 263

    • M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the S1D13504 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 13504PWR.EXE to a directory that is in the DOS path on your hard...

  • Page 264

    Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13504pwr [/software  /lcd] [/enable  /disable] [/i] [/?]. Embedded platform: execute 13504pwr and at the prompt, type the command line argument. Where: selects software suspend...

  • Page 265

    13504CFG configuration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. 13504PWR Software Suspend Power Sequencing Utility...

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    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A-B-007-04 Issue Date: 01/02/01...

  • Page 267

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 268

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Driver Configuration Program X19A-B-008-03 Issue Date: 01/10/26...

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    Epson Research and Development Page 3 Vancouver Design Center Table of Contents 13504DCFG ..........5 Installation .

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    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Driver Configuration Program X19A-B-008-03 Issue Date: 01/10/26...

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    Note It is possible to override recommended register settings and select incorrect panel tim- ings using 13504DCFG. Seiko Epson does not assume liability for any damage done to the display device as a result of configuration errors. 13504DCFG Driver Configuration Program...

  • Page 272

    Page 6 Epson Research and Development Vancouver Design Center Installation Create a directory for 13504dcfg.exe. Copy the files 13504dcfg.exe and panels.def to that directory. Panels.def contains configuration information for a number of panels and must reside in the same directory as 13504dcfg.exe.

  • Page 273

    Display Buffer Address CPU Data Bus Width The General tab contains S1D13504 evaluation platform specific information. The values presented are used for configuring HAL based display drivers. The settings on this tab specify where in CPU address space the registers and display buffer are located and the data bus size.

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    Page 8 Epson Research and Development Vancouver Design Center these addresses select the User-Defined option and enter the correct addresses for “Register address” and “Display buffer address”. Register Address The physical address of the start of register decode space (in hexadecimal).

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    Epson Research and Development Page 9 Vancouver Design Center Preferences Tab Initial Display Panel Color Depth The Preference tab contains settings pertaining to the initial display state. During runtime the display surface or color depth may be changed by software.

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    Memory Clock The current Memory Clock (MCLK) frequency is displayed here. Access Time Selects the access time of the DRAM. The S1D13504 evaluation boards use 50ns DRAM. S1D13504 13504DCFG Driver Configuration Program X19A-B-008-03 Issue Date: 01/10/26...

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    Memory Type Selects the memory type, either Extended Data Out (EDO) or Fast Page Mode (FPM). The S1D13504 evaluation boards use EDO DRAM. WE# Control Selects the WE# control used for the DRAM. DRAM uses one of two methods of control when writing to memory.

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    Page 12 Epson Research and Development Vancouver Design Center Installed Memory Selects the amount of DRAM available for the display buffer. The S1D13504 evaluation boards have 2M bytes of DRAM installed. S1D13504 13504DCFG Driver Configuration Program X19A-B-008-03 Issue Date: 01/10/26...

  • Page 279

    MCLK Divide The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13504 Hardware Functional Specification, document number X19A-B-001-xx. Note Changing clock values may modify or invalidate Panel or CRT settings.

  • Page 280

    Page 14 Epson Research and Development Vancouver Design Center Actual This field displays the CLKI frequency that 13A04DFG will use for configuration calculations. BUSCLK These controls are used to inform 13A04DCFG of the clock frequency attached to BUSCLK. Setting incorrect BUSCLK values result in errors in the rest of the configuration process.

  • Page 281

    Panels TFT/FPLINE Non-Display TFT/FPFRAME Period The S1D13504 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type Selects between passive (STN) and active (TFT) panel types. Several options may change or become unavailable when the STN/TFT setting is switched.

  • Page 282

    Selects the data format for color STN panel Data Format 2. This option is only available for configuring 8-bit color STN panels. See the S1D13504 Hardware Functional Specification, document number X19A-B-001-xx, for description of Data Format 1 / Data Format 2. Most panels use Data Format 2.

  • Page 283

    TFT/FPLINE (pixels) These settings allow fine tuning the TFT line pulse parameters and are only available when the selected panel type is TFT. Refer to S1D13504 Hardware Functional Specification, document number X19A-B- 001-xx for a complete description of the FPLINE pulse settings.

  • Page 284

    Page 18 Epson Research and Development Vancouver Design Center Pulse width Specifies the pulse width (in lines) of the FPFRAME output signal. Predefined Panels 13504DCFG uses a file (panels.def) which lists various panel manufacturers recommended settings. If the file panels.def is present in the same directory as 13504dcfg.exe, the settings for a number of predefined...

  • Page 285

    (height) of the images. If both displays are the same resolution, select “Normal”. Otherwise, refer to the S1D13504 Hardware Functional Specification, document number X19A-B-001-xx for information on selecting the best option.

  • Page 286

    Vancouver Design Center Registers Tab The Registers tab allows viewing and direct editing the S1D13504 register values. Scroll up and down the list of registers and view their configured value. Hovering the mouse pointer over a register line will pop up a tooltip containing a breakdown of the contents of that register.

  • Page 287

    “Preview” button starts Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13504 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button.

  • Page 288

    The pop-up menu is used to select the delay before the tooltip appears. ERD on the Web This “Help” menu item is a hotlink to the Epson Research and Development website. Selecting “Help” then “ERD on the Web” starts the default web browser and points it to the ERD web site.

  • Page 289

    Comments • It is possible to override recommended register settings and select incorrect timings using 13504DCFG. Seiko Epson does not assume liability for any damage done to the display device as a result of configuration errors. • On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13504.

  • Page 290

    Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 13504DCFG Driver Configuration Program X19A-B-008-03 Issue Date: 01/10/26...

  • Page 291

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 292

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Windows® CE 2.x Display Drivers X19A-E-001-05 Issue Date: 01/05/25...

  • Page 293

    Vancouver Design Center WINDOWS® CE 2.x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13504 Color Graphics LCD/CRT Controller running under the Microsoft Windows CE 2.x operating system. The driver is capable of 4, 8 and 16 bit-per-pixel display modes.

  • Page 294

    Click on “Shortcut” and replace the string “DEMO1” under the entry “Target” with “DEMO7”. Click on “OK” to finish. 5. Create a sub-directory named S1D13504 under x:\wince\platform\cepc\drivers\dis- play. 6. Copy the source code to the S1D13504 subdirectory. S1D13504 Windows® CE 2.x Display Drivers X19A-E-001-05 Issue Date: 01/05/25...

  • Page 295

    8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the de- fault display driver to the file EPSON.DLL (EPSON.DLL will be created during the build in step 13). Replace or comment out the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll...

  • Page 296

    2. Install Microsoft Visual C/C++ version 5.0 or 6.0. 3. Install Platform Builder 2.1x by running SETUP.EXE from compact disk #1. 4. Follow the steps below to create a “Build Epson for x86” shortcut which uses the current “Minshell” project icon/shortcut on the Windows desktop.

  • Page 297

    Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right clicking on the icon and choosing “rename”. g. Right click on the icon “Build Epson for x86” and click on “Properties” to bring up the “Build Epson for x86 Properties” window.

  • Page 298

    13504CFG, refer to the 13504CFG Configuration Program User Manual, document number X19A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13504 WinCE Drivers”. Save the new configuration as MODE0.H in x:\wince\platform\cepc\drivers\display\S1D13504, replacing the original configura- tion file.

  • Page 299

    12. Generate the proper building environment by double-clicking on the Epson project icon --”Build Epson for x86”. 13. Type BLDDEMO <ENTER> at the command prompt of the “Build Epson for x86” window to generate a Windows CE image file (NK.BIN).

  • Page 300

    Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.

  • Page 301

    Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13504 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.

  • Page 302

    Page 12 Epson Research and Development Vancouver Design Center Mode File A second variable which will affect the finished display driver is the register configurations contained in the mode file. The MODE tables (contained in files MODE0.H, MODE1.H, MODE2.H . . .) contain register information to control the desired display mode.

  • Page 303

    Epson Research and Development Page 13 Vancouver Design Center Comments • The display driver is CPU independent, allowing use of the driver for several Windows CE Platform Builder supported platforms. • When using 13504CFG.EXE to produce multiple MODE tables, make sure you change the Mode Number in the WinCE tab for each mode table you generate.

  • Page 304

    Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Windows® CE 2.x Display Drivers X19A-E-001-05 Issue Date: 01/05/25...

  • Page 305

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 306

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River WindML v2.0 Display Drivers X19A-E-002-03 Issue Date: 01/04/06...

  • Page 307

    The source code is written for portability and contains functionality for most features of the S1D13504. Source code modification is required to provide a smaller, more efficient driver for mass production (e.g. CRT support may be removed for products not requiring a CRT).

  • Page 308

    Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2.0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program. These instructions assume that Wind River’s Tornado platform is already installed.

  • Page 309

    Mode0.h should be created using the configuration utility 13504DCFG. For more infor- mation on 13504DCFG, see the 13504DCFG Configuration Program User Manual, document number X19A-B-008-xx available at www.erd.epson.com. 7. Open the S1D13504 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13504\8bpp\13504.wsp”...

  • Page 310

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River WindML v2.0 Display Drivers X19A-E-002-03 Issue Date: 01/04/06...

  • Page 311

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 312

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River UGL v1.2 Display Drivers X19A-E-003-02 Issue Date: 01/02/01...

  • Page 313

    Vancouver Design Center Wind River UGL v1.2 Display Drivers The Wind River UGL v1.2 display drivers for the S1D13504 Color Graphics LCD/CRT Controller are intended as “reference” source code for OEMs developing for Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13504.

  • Page 314

    Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1.2 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo software. These instructions assume that the Wind River Tornado platform is correctly installed.

  • Page 315

    Mode0.h should be created using the configuration utility 13504DCFG. For more infor- mation on 13504DCFG, see the 13504DCFG Configuration Program User Manual, document number X19A-B-008-xx available at www.erd.epson.com. 6. Open the S1D13504 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13504\8bpp\13504.wsp”...

  • Page 316

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Wind River UGL v1.2 Display Drivers X19A-E-003-02 Issue Date: 01/02/01...

  • Page 317

    Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.

  • Page 318

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Linux Console Driver X19A-E-004-01 Issue Date: 01/11/19...

  • Page 319

    Page 3 Vancouver Design Center Linux Console Driver The Linux console driver for the S1D13504 Embedded Memory LCD Controller is intended as “reference” source code for OEMs developing for Linux, and supports 4 and 8 bit-per-pixel color depths. A Graphical User Interface (GUI) such as Gnome can obtain the frame buffer address from this driver allowing the Linux GUI the ability to update the display.

  • Page 320

    Before continuing with modifications for the S1D13504, you should ensure that you can build and start the Linux operating system. 2. Unzip the console driver files. Using a zip file utility, unzip the S1D13504 archive to a temporary directory. (e.g. /tmp) When completed the files: s1d13xxxfb.c...

  • Page 321

    If your kernel version is not 2.2.17 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names.

  • Page 322

    Note In order to use the S1D13504 console driver with X server, you need to configure the X server to use the FBDEV device. A good place to look for the necessary files and in- structions on this process is on the Internet at www.xfree86.org...

  • Page 323

    Before continuing with modifications for the S1D13504, you should ensure that you can build and start the Linux operating system. 2. Unzip the console driver files. Using a zip file utility, unzip the S1D13504 archive to a temporary directory. (e.g. /tmp) When completed the files: Config.in...

  • Page 324

    If your kernel version is not 2.4.5 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names.

  • Page 325

    Note In order to use the S1D13504 console driver with X server, you need to configure the X server to use the FBDEV device. A good place to look for the necessary files and in- structions on this process is on the Internet at www.xfree86.org...

  • Page 326

    Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Linux Console Driver X19A-E-004-01 Issue Date: 01/11/19...

  • Page 327

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.

  • Page 328

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Windows® CE 3.x Display Drivers X19A-E-006-01 Issue Date: 01/05/08...

  • Page 329

    Vancouver Design Center WINDOWS® CE 3.x DISPLAY DRIVERS The Windows CE 3.x display driver is designed to support the S1D13504 Color Graphics LCD/CRT Controller running the Microsoft Windows CE operating system, version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel display modes.

  • Page 330

    Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for: 1. Windows CE Platform Builder 3.00 using the GUI interface. 2. Windows CE Platform Builder 3.00 using the command-line interface.

  • Page 331

    Click the Set button. Click the OK button. 7. Create a new directory S1D13504, under x:\wince300\platform\cepc\drivers\display, and copy the S1D13504 driver source code into this new directory. 8. Add the S1D13504 driver component. a. From the Platform menu, select “Insert | User Component”.

  • Page 332

    X19A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13504 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 12. From the Platform window, click on ParameterView Tab. Show the tree for MY- PLATFORM Parameters by clicking on the ‘+’...

  • Page 333

    CEPC_DDI_S1D13X0X=1 4. Generate the build environment by calling cepath.bat. 5. Create a new folder called S1D13504 under x:\wince300\platform\cepc\drivers\dis- play, and copy the S1D13504 driver source code into x:\wince300\platform\cepc\driv- ers\display\S1D13504. 6. Edit the file x:\wince300\platform\cepc\drivers\display\dirs and add S1D13504 into the list of directories.

  • Page 334

    X19A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13504 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 9. Edit the file PLATFORM.REG to match the screen resolution, color depth, and rota- tion information in MODE.H.

  • Page 335

    Epson Research and Development Page 9 Vancouver Design Center 10. Delete all the files in the x:\wince300\release directory and delete the file x:\wince300\platform\cepc\*.bif 11. Type BLDDEMO <ENTER> at the command prompt to generate a Windows CE image file. The file generated will be x:\wince300\release\nk.bin.

  • Page 336

    Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.

  • Page 337

    Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13504 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.

  • Page 338

    Page 12 Epson Research and Development Vancouver Design Center DEBUG_MONITOR This option enables the use of the debug monitor. The debug monitor can be invoked when the display driver is first loaded and can be used to view registers, and perform a few debugging tasks.

  • Page 339

    Epson Research and Development Page 13 Vancouver Design Center Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch = 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When the display driver starts, it will read these values in the registry and attempt to match a mode table against them.

  • Page 340

    To enable or disable the use of off-screen memory, edit the file: x:\wince300\platform\cepc\driv- ers\display\S1D13504\sources. In SOURCES, there is a line which, when uncom- mented, will instruct Windows CE to use off-screen display memory (if sufficient...

  • Page 341

    Windows CE is shut down. If dis- play memory is kept powered up (set the S1D13504 in powersave mode), then the dis- play data will be maintained and this step can be skipped.

  • Page 342

    Page 16 Epson Research and Development Vancouver Design Center Comments • The display driver is CPU independent, allowing use of the driver for several Windows CE Platform Builder supported platforms. • If you are running 13504CFG.EXE to produce multiple MODE tables, make sure you change the Mode Number in the WinCE tab for each mode table you generate.

  • Page 343

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners...

  • Page 344

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32-Bit Windows Device Driver Installation Guide X00A-E-003-04 Issue Date: 01/04/17...

  • Page 345

    This manual describes the installation of the Windows 9x/ME/NT 4.0/2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards. The file S1D13XXX.VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x/ME.

  • Page 346

    Type the driver location or select BROWSE to find it. 7. Click NEXT. 8. Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card. Select this file and click OPEN. 9. Windows then shows the path to the file. Click OK.

  • Page 347

    Type the driver location or select BROWSE to find it. 5. Click NEXT. 6. Windows will open the installation file and show the option EPSON PCI Bridge Card. 7. Click FINISH. All ISA Bus Evaluation Cards 1.

  • Page 348

    8. Select OTHER DEVICES from HARDWARE TYPE and Click NEXT. 9. Click HAVE DISK. 10. Specify the location of the driver and click OK. 11. Click OK. 12. EPSON PCI Bridge Card will appear in the list. 13. Click NEXT. 14. Windows will install the driver. 15. Click FINISH.

  • Page 349

    Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards 1. Install the evaluation board in the computer and boot the computer. 2. Go to the CONTROL PANEL and select ADD NEW HARDWARE. 3. Click NEXT.

  • Page 350

    7. Specify the location of the driver files and click OK. 8. Select the file S1D13XXX.INF and click OK. 9. Click OK. 10. The EPSON PCI Bridge Card should be selected in the list window. 11. Click NEXT. 12. Click NEXT.

  • Page 351

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 352

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 353

    Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ......... . . 7 Features .

  • Page 354

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 355

    Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2-1: Configuration DIP Switch Settings ........8 Table 2-2: Host Bus Selection .

  • Page 356

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 357

    This manual describes the setup and operation of the S5U13504B00C Rev. 1.0 Evaluation Board when used with the S1D13504 Color Graphics LCD/CRT Controller in the ISA bus environment. For more information regarding the S1D13504, refer to the S1D13504 Hardware Functional Speci- fication, document number X19A-A-002-xx.

  • Page 358

    Vancouver Design Center 2 Installation and Configuration The S1D13504 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. S1D13504 configuration inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one five-position DIP switch is provided for this purpose. All remaining config- uration inputs are hard-wired.

  • Page 359

    Epson Research and Development Page 9 Vancouver Design Center 3 LCD / RAMDAC Interface Pin Mapping Table 3-1: LCD Signal Connector (J6) Color TFT Color Passive Mono Passive External S1D13504 Connector RAMDAC Pin Names Pin No. 9-bit 12-bit 18-bit 4-bit...

  • Page 360

    4 CPU / BUS Interface Connector Pinouts Table 4-1: CPU/BUS Connector (H1) Pinout Connector Comments Pin No. Connected to DB0 of the S1D13504 Connected to DB1 of the S1D13504 Connected to DB2 of the S1D13504 Connected to DB3 of the S1D13504 Ground...

  • Page 361

    Table 4-2: CPU/BUS Connector (H2) Pinout Connector Comments Pin No. Connected to AB0 of the S1D13504 Connected to AB1 of the S1D13504 Connected to AB2 of the S1D13504 Connected to AB3 of the S1D13504 Connected to AB4 of the S1D13504...

  • Page 362

    Page 12 Epson Research and Development Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5-1: Host Bus Interface Pin Mapping S1D13504 SH-3 MC68K Bus 1 MC68K Bus 2 Generic MPU Pin Names AB[20:1] A[20:1] A[20:1] A[20:1] A[20:1] LDS#...

  • Page 363

    D00000h to enable a 16-bit ISA environment. This must be done prior to initializing the S1D13504. Failure to do so will result in the S1D13504 being configured as a 16-bit device (de- fault, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an 8-bit interface.

  • Page 364

    CMOS level output drive of the S1D13504. 6.3 DRAM Support The S1D13504 supports 256K x 16 as well as 1M x 16 DRAM (FPM and EDO) in symmetrical and asymmetrical formats. The S5U13504B00C board supports 5.0V 1M x 16 EDO-DRAM (42-pin SOJ package) in symmet- rical format, providing a 2M byte display buffer.

  • Page 365

    The S1D13504 cannot support 12 or 18-bit TFT panels when CRT is enabled. FPDAT [15:8] is used for RAMDAC data and is not available for LCD. Refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx for details.

  • Page 366

    The signal VLCD can be adjusted by R37 to supply an output voltage from -14V to -23V and is enabled/disabled by the S1D13504 control signal LCDPWR. Determine the panel’s specific power requirements and set the potentiometer accordingly before connecting the panel.

  • Page 367

    Vancouver Design Center 6.15 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13504 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus. Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout,” on page 10 and Table 4-2 “CPU/BUS Connector (H2) Pinout,”...

  • Page 368

    Page 18 Epson Research and Development Vancouver Design Center 7 Parts List Item # Qty/board Designation Part Value Description C13, C14, C19, 10uF 10uF/25V Tantalum D-Size C1-C12, C15-C18 0.01uF 0.01uF, 1206 package C20, C21, C30 0.1uF 0.1uF, 1206 package C23-C25...

  • Page 369

    Epson Research and Development Page 19 Vancouver Design Center Item # Qty/board Designation Part Value Description NEC 1Mx16 , EDO, Self-Refresh, DRAM, SOJ UPD4218S165LE-50 package TIBPAL22V10-15BCNT Texas Instrument PAL 24 pin DIP package/socketed Osc. -14 Fox 40.0MHz Oscillator or equiv. 14 pin DIP/socketed...

  • Page 370

    Page 20 Epson Research and Development Vancouver Design Center 8 Schematic Diagrams Figure 1: S1D13504B00C Schematic Diagram (1 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 371

    Epson Research and Development Page 21 Vancouver Design Center Figure 2: S1D13504B00C Schematic Diagram (2 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...

  • Page 372

    Page 22 Epson Research and Development Vancouver Design Center Figure 3: S1D13504B00C Schematic Diagram (3 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 373

    Epson Research and Development Page 23 Vancouver Design Center Figure 4: S1D13504B00C Schematic Diagram (4 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...

  • Page 374

    Page 24 Epson Research and Development Vancouver Design Center Figure 5: S1D13504B00C Schematic Diagram (5 of 6) S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 375

    Epson Research and Development Page 25 Vancouver Design Center Figure 6: S1D13504B00C Schematic Diagram (6 of 6) S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504 Issue Date: 01/02/02 X19A-G-004-06...

  • Page 376

    Page 26 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-06 Issue Date: 01/02/02...

  • Page 377

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.

  • Page 378

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 379

    Technical Support ........31 EPSON LCD/CRT Controllers (S1D13504) .

  • Page 380

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 381

    Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3-1: Configuration DIP Switch Settings ......9 Table 3-2: Jumper Settings .

  • Page 382

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 383

    1 Introduction This manual describes the setup and operation of the S5U13504B00C Rev. 2.0 PCI Evalu- ation Board. The S5U13504B00C is designed as an evaluation platform for the S1D13504 Color LCD Controller chip. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development.

  • Page 384

    • 1Mx16 EDO DRAM. • Configuration options. • Headers for S1D13504 current consumption measurements. • Adjustable positive LCD bias power supplies from +24V to +40V. • Adjustable negative LCD bias power supplies from -23V to -14V.

  • Page 385

    The S5U13504B00C is designed to support as many platforms as possible. The S5U13504B00C incorporates a DIP switch and several jumpers which allow both evalu- ation board and S1D13504 LCD controller settings to be configured for a specified evalu- ation platform.

  • Page 386

    Page 10 Epson Research and Development Vancouver Design Center 3.2 Configuration Jumpers The S5U13504B00C has seven jumper blocks which configure various board settings. The jumper positions for each function are shown below. Table 3-2: Jumper Settings Jumper Function Position 1-2...

  • Page 387

    BUSCLK Figure 3-3: Configuration Jumper (JP2) Location JP3 - CoreVDD Current JP3 allows the mesurement of S1D13504 CoreVDD current consumption. When the jumper is at position 1-2, the evaluation board is operating normally (default setting). When no jumper is installed, CoreVDD current comsumption can be measured by connecting an ampmeter to JP3.

  • Page 388

    Epson Research and Development Vancouver Design Center JP4 - IOVDD Current JP4 allows the mesurement of S1D13504 IOVDD current consumption. When the jumper is at position 1-2, the evaluation board is operating normally (default setting). When no jumper is installed, IOVDD current comsumption can be measured by connecting an ampmeter to JP4.

  • Page 389

    Epson Research and Development Page 13 Vancouver Design Center JP6 - Panel Enable Polarity JP6 selects the polarity of the LCDPWR panel enable signal. When the jumper is at position 1-2, the LCDPWR signal is active high (default setting). When the jumper is at position 2-3, the LCDPWR signal is active low.

  • Page 390

    Page 14 Epson Research and Development Vancouver Design Center 4 Technical Description The S5U13504B00C operates with both PCI and non-PCI evaluation platforms. It supports passive LCD panels (4/8/16-bit) and TFT/D-TFD panels (9/12/18-bit). 4.1 PCI Bus Support The S5U13504B00C does not have on-chip PCI bus interface support. The S5U13504B00C uses the PCI FPGA to support the PCI bus.

  • Page 391

    Epson Research and Development Page 15 Vancouver Design Center 4.2.1 CPU Interface Pin Mapping The functions of the S1D13504 host interface pins are mapped to each host bus interface according to the following table. Table 4-1: CPU Interface Pin Mapping S1D13504...

  • Page 392

    The pinouts for Connector H1 are listed in the following table. Table 4-2: CPU/BUS Connector (H1) Pinout Pin No. Function Connected to DB0 of the S1D13504 Connected to DB1 of the S1D13504 Connected to DB2 of the S1D13504 Connected to DB3 of the S1D13504...

  • Page 393

    +5 volt supply, required in non-PCI applications Connected to RD/WR# of the S1D13504 Connected to BS# of the S1D13504 Connected to S1D13504 BUSCLK if JP1 is in position 2-3 Connected to RD# of the S1D13504 Connected to AB20 of the S1D13504 Not Connected S5U13504B00C Rev.

  • Page 394

    The interface signals are alternated with grounds on the cable to reduce cross-talk and noise. When supporting an 18-bit TFT/D-TFD panel, the S1D13504 can display 64K of a possible 256K colors because only 16 of the 18 bits of LCD data are available from the S1D13504.

  • Page 395

    Panel Enable, active low or active high according to JP6 = Driven low Note For FPDATxx to LCD interface hardware connections refer to the Display Interface AC Timing section of the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx. S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual S1D13504...

  • Page 396

    Vancouver Design Center 4.3.2 Buffered LCD Connector J1 provides the same LCD panel signals as those directly from S1D13504, but with voltage- adapting buffers which can be set to 3.3V or 5V. Pin 32 on this connector provides power for the LCD panel logic at the same voltage as the buffer power supply.

  • Page 397

    4.4 Current Consumption Measurement The evaluation board has 2 headers, JP3 and JP4, which allow the independent measurement of S1D13504 CoreVDD and IOVDD current consumption. To measure the current, remove the appropriate jumper and connect an ammeter to the corresponding header pins.

  • Page 398

    5 References 5.1 Documents • Epson Research and Development, Inc., S1D13504 Hardware Functional Specification, document number X19A-A-001-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, document number X19A-G-002-xx. 5.2 Document Sources • Epson Research and Development Website: http://www.erd.epson.com.

  • Page 399

    Epson Research and Development Page 23 Vancouver Design Center 6 Parts List Table 6-1: Parts List Manufacturer / Part No. / Assembly Item Reference Part Description Instructions C1,C2,C3,C4, C5,C6,C7,C8, C9,C11,C12, C13,C14,C15, C16,C19,C21, C0805 0.1uF Panasonic ECJ-2VB1C104K (generic) C22,C23,C29, C30,C31,C32, C33,C34,C35,...

  • Page 400

    Page 24 Epson Research and Development Vancouver Design Center Table 6-1: Parts List Manufacturer / Part No. / Assembly Item Reference Part Description Instructions R22,R19 R0805 100K generic R0805 1.2M generic R0805 generic R24,R25,R30 R0805 1K,5% generic DIPSW5 S1D13504 Config...

  • Page 401

    Epson Research and Development Page 25 Vancouver Design Center 7 Schematics Figure 7-1: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (1 of 5) S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual S1D13504 Issue Date: 2002/12/02 X19A-G-014-01...

  • Page 402

    Page 26 Epson Research and Development Vancouver Design Center Figure 7-2: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (2 of 5) S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 403

    Epson Research and Development Page 27 Vancouver Design Center Figure 7-3: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (3 of 5) S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual S1D13504 Issue Date: 2002/12/02 X19A-G-014-01...

  • Page 404

    Page 28 Epson Research and Development Vancouver Design Center Figure 7-4: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (4 of 5) S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 405

    Epson Research and Development Page 29 Vancouver Design Center Figure 7-5: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (5 of 5) S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual S1D13504 Issue Date: 2002/12/02 X19A-G-014-01...

  • Page 406

    Page 30 Epson Research and Development Vancouver Design Center 8 Board Layout Figure 8-1: S5U13504B00C Rev. 2.0 Evaluation Board Layout S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 407

    Epson Research and Development Page 31 Vancouver Design Center 9 Technical Support 9.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 408

    Page 32 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual X19A-G-014-01 Issue Date: 2002/12/02...

  • Page 409

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 410

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-09 Issue Date: 01/10/26...

  • Page 411

    Interfacing to the PR31500/PR31700 ......8 S1D13504 Host Bus Interface ......9 Generic MPU Host Bus Interface Pin Mapping .

  • Page 412

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-09 Issue Date: 01/10/26...

  • Page 413

    Table 5-2: PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E ..19 Table 5-3: S1D13504 Configuration using the IT8368E ..... . . 20 Table 5-4: S1D13504 Host Bus Selection using the IT8368E.

  • Page 414

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-09 Issue Date: 01/10/26...

  • Page 415

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Philips MIPS PR31500/PR31700 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 416

    2 Interfacing to the PR31500/PR31700 The Philips PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13504 connects to the PR31500/PR31700 processor. The S1D13504 can be successfully interfaced using one of three configurations: •...

  • Page 417

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 418

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 419

    Oscillator CLKI Note: When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection Note For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.

  • Page 420

    The S1D13504 also has internal clock dividers providing additional flexibility. 4.2 Memory Mapping and Aliasing The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the PR31500/PR31700) to the M/R# input of the S1D13504.

  • Page 421

    Vancouver Design Center 4.3 S1D13504 Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

  • Page 422

    S1D13504 can be interfaced with the PR31500/PR31700 without using a PC Card slot. Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot.

  • Page 423

    Asynchronous Timing (for details refer to the S1D13504 Hardware Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

  • Page 424

    Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether...

  • Page 425

    Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

  • Page 426

    When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13504. When accessing the S1D13504 the associated card-side signals are disabled in order to avoid any conflicts.

  • Page 427

    When the PR31500/PR31700 accesses the PC Card slots buffered through the ITE IT8368E, bits CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the PR31500/PR31700 is divided into Attribute, IO and S1D13504 access. Table 5-2:, “PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E” provides all the details of the Attribute/IO address re-allocation by the IT8368E.

  • Page 428

    Vancouver Design Center 5.5 S1D13504 Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

  • Page 429

    Vancouver Design Center 6 Software Test utilities and display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 430

    • Epson Research and Development, Inc., S1D13504 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.

  • Page 431

    Epson Research and Development Page 23 Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 432

    Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Philips MIPS PR31500/PR31700 Processor X19A-G-005-09 Issue Date: 01/10/26...

  • Page 433

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 434

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Power Consumption X19A-G-006-04 Issue Date: 01/02/02...

  • Page 435

    – the higher the divide, the lower the power consumption. There are two power save modes in the S1D13504: Software and Hardware SUSPEND. The power consumption of these modes is also affected by various system design variables.

  • Page 436

    LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13504 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.

  • Page 437

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 438

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-08 Issue Date: 01/10/26...

  • Page 439

    LCD Memory Access Cycles ......9 S1D13504 Host Bus Interface ......10 Generic MPU Host Bus Interface Pin Mapping .

  • Page 440

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-08 Issue Date: 01/10/26...

  • Page 441

    Table 4-2: Host Bus Interface Selection ....... . 13 Table 4-2: NEC/S1D13504 Truth Table ....... . 14 List of Figures Figure 2-1: NEC VR4102 Read/Write Cycles .

  • Page 442

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-08 Issue Date: 01/10/26...

  • Page 443

    Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the NEC 4102 Microprocessor (uPD30102). The NEC V 4102 Microprocessor is specifically...

  • Page 444

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2.1 The NEC VR4102 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE-based embedded consumer applications in mind, the VR4102 offers a highly integrated solution for portable systems.

  • Page 445

    Epson Research and Development Page 9 Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle.

  • Page 446

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 447

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 448

    Notes: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec. When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

  • Page 449

    Vancouver Design Center 4.2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

  • Page 450

    The V 4102™ uses a read, write and system high-byte enable to interface to an external LCD controller. The S1D13504 uses low and high byte read and write strobes and therefore minimal “glue” logic is necessary. Table 4-2: NEC/S1D13504 Truth Table...

  • Page 451

    Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 452

    • Epson Research and Development, Inc., S1D13504 Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.

  • Page 453

    Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 454

    Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-08 Issue Date: 01/10/26...

  • Page 455

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.

  • Page 456

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MC68328 "Dragonball" Microprocessor X19A-G-013-03 Issue Date: 01/10/26...

  • Page 457

    Chip-Select Module ......8 S1D13504 Host Bus Interface ......9 Generic MPU Host Bus Interface Pin Mapping .

  • Page 458

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MC68328 "Dragonball" Microprocessor X19A-G-013-03 Issue Date: 01/10/26...

  • Page 459

    Table 4-1: Summary of Power-On/Reset Options ......13 Table 4-2: S1D13504 Host Bus Selection ....... 13 Table 4-3: Memory Configuration .

  • Page 460

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MC68328 "Dragonball" Microprocessor X19A-G-013-03 Issue Date: 01/10/26...

  • Page 461

    S1D13504 Color Graphics LCD/CRT Controller and the Motorola MC68328 ‘Dragonball’ Microprocessor. By implementing a dedicated display refresh memory, the S1D13504 can reduce system power consumption, improve image quality, and increase system performance as compared to the Dragonball’s on-chip LCD controller.

  • Page 462

    The S1D13504 implements the MC68000 bus interface using its MC68000 Bus 1 mode, so this mode may be used to connect the 68328 directly to the S1D13504 with no glue logic. However, several of the 68000 bus control signals are multiplexed with I/O and interrupt signals on the 68328, and in many applications it may be desirable to make these pins available for these alternate functions.

  • Page 463

    Generic MPU host bus interface used to implement the interface to the MC68328. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 464

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 465

    S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Block Diagram of MC68328 to S1D13504 Interface - MC68000 Bus 1 Interface Mode Interfacing to the Motorola MC68328 "Dragonball" Microprocessor...

  • Page 466

    Figure 4-2: Block Diagram of MC68328 to S1D13504 Interface - Generic Interface Mode The S1D13504 requires a 2M byte address space for the display buffer, plus a few more locations to access its internal registers. To accommodate this relatively large block size, it is preferable to use one of the chip selects from groups A or B, but this is not required.

  • Page 467

    Vancouver Design Center 4.2 S1D13504 Hardware Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 4-2 shows the settings used for the S1D13504 in these interfaces. MD1, MD2, and MD3 should be set to select either MC68000 Bus 1 mode or Generic bus mode as desired.

  • Page 468

    Asymmetrical 1M x 16 DRAM 4.3 MC68328 Chip Select Configuration In the example interface, chip select CSB3 is used to control the S1D13504. A 4M byte address space is used. The S1D13504 control registers are mapped into the bottom half of this address block, while the display buffer is mapped into the top half.

  • Page 469

    Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 470

    Motorola Publication no. MC68328UM/AD. • Epson Research and Development, Inc., S1D13504 Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx.

  • Page 471

    Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 472

    Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MC68328 "Dragonball" Microprocessor X19A-G-013-03 Issue Date: 01/10/26...

  • Page 473

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 474

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the PC Card Bus X19A-G-009-05 Issue Date: 01/02/02...

  • Page 475

    Memory Access Cycles ....... . . 8 S1D13504 Host Bus Interface ......10 Generic MPU Host Bus Interface Pin Mapping .

  • Page 476

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the PC Card Bus X19A-G-009-05 Issue Date: 01/02/02...

  • Page 477

    Figure 2-2: PC Card Write Cycle ........9 Figure 4-1: Typical Implementation of PC Card to S1D13504 Interface ....12...

  • Page 478

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the PC Card Bus X19A-G-009-05 Issue Date: 01/02/02...

  • Page 479

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 480

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1...

  • Page 481

    Epson Research and Development Page 9 Vancouver Design Center During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle.

  • Page 482

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 483

    The Generic MPU host bus interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 484

    RD/WR#, WE0#, WE1#, and CS# for the S1D13504. The PAL also inverts the reset signal of the PC card since it is active high and the S1D13504 uses an active low reset. PAL equations for this implementation are listed in Section 4.3,“PAL Equations” on page 14.

  • Page 485

    Vancouver Design Center 4.2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

  • Page 486

    ; inversion appears in pin declaration section 4.4 Register/Memory Mapping The S1D13504 is a memory mapped device. The internal registers are mapped in the lower PC Card memory address space starting at zero. The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card memory address space (ranging from 200000h to 3fffffh).

  • Page 487

    Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 488

    • PCMCIA/JEIDA, PC Card Standard -- March 1997 • Epson Research and Development, Inc., S1D13504 Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx.

  • Page 489

    Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 490

    Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the PC Card Bus X19A-G-009-05 Issue Date: 01/02/02...

  • Page 491

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 492

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-06 Issue Date: 01/10/26...

  • Page 493

    User-Programmable Machine (UPM) ......12 S1D13504 Host Bus Interface ......13 Generic MPU Host Bus Interface Pin Mapping .

  • Page 494

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-06 Issue Date: 01/10/26...

  • Page 495

    Table 3-1: Generic MPU Host Bus Interface Pin Mapping ..... . 13 Table 4-1: List of Connections from MPC821ADS to S1D13504 ....16 Table 4-2: Summary of Power-On/Reset Options .

  • Page 496

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-06 Issue Date: 01/10/26...

  • Page 497

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Motorola MPC821 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 498

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2.1 The MPC8xx System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.

  • Page 499

    Epson Research and Development Page 9 Vancouver Design Center 2.2.1 Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: •...

  • Page 500

    Page 10 Epson Research and Development Vancouver Design Center The following figure illustrates a typical memory write cycle on the Power PC system bus. SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Valid Transfer Start Wait States Transfer Next Transfer Complete Starts...

  • Page 501

    S1D13504, therefore the interfaces described in this document do not attempt to support burst cycles. However, the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13504 address space. 2.3 Memory Controller Module 2.3.1 General-Purpose Chip Select Module (GPCM)

  • Page 502

    In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibility to accommodate the S1D13504 and it is desirable to leave the UPM free to handle other interfacing duties, such as EDO DRAM.

  • Page 503

    MPC821 General-Purpose Chip Select Module. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 504

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 505

    4 MPC821 to S1D13504 Interface 4.1 Hardware Description The interface between the S1D13504 and the MPC821 requires no glue logic. All lines are directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.

  • Page 506

    4.2 Hardware Connections The following table details the connections between the pins and signals of the MPC821 and the S1D13504. Table 4-1: List of Connections from MPC821ADS to S1D13504 MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13504 Signal Name...

  • Page 507

    Epson Research and Development Page 17 Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13504 (Continued) MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13504 Signal Name P12-B14 P12-D14 P12-B13 P12-C13 SRESET P9-D15 RESET# SYSCLK P9-C2 BUSCLK...

  • Page 508

    Vancouver Design Center 4.3 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

  • Page 509

    Chip select 4 is used to control the S1D13504. The following options are selected in the base address register (BR4): • BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13504 to 40 0000h. • AT[0:2] = 0 – ignore address type bits.

  • Page 510

    The test software used to exercise this interface is very simple. It carries out the following functions: 1. Configures chip select 4 on the MPC821 to map the S1D13504 to an unused 4M byte block of address space. 2. Loads the appropriate values into the option register for CS4.

  • Page 511

    S1D13504 memory block is tagged as non-cacheable. This ensures that accesses to the S1D13504 will occur in proper order, and the MPC821 will not attempt to cache any data read from or written to the S1D13504 or its display buffer.

  • Page 512

    Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 513

    • Epson Research and Development, Inc., S1D13504 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.

  • Page 514

    Page 24 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 515

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 516

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor X19A-G-011-07 Issue Date: 01/02/02...

  • Page 517

    Chip-Select Module ......10 S1D13504 Bus Interface ....... . 11 Generic MPU Host Bus Interface Pin Mapping .

  • Page 518

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor X19A-G-011-07 Issue Date: 01/02/02...

  • Page 519

    Table 4-1: S1D13504 Configuration Settings ......14 Table 4-2: S1D13504 Host Bus Selection ....... 14 List of Figures Figure 2-1: MCF5307 Memory Read Cycle .

  • Page 520

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor X19A-G-011-07 Issue Date: 01/02/02...

  • Page 521

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Motorola MCF5307 “Coldfire” microprocessor. The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption.

  • Page 522

    Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2.1 The MCF5307 System Bus The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. This section provides an overview of the operation of the MCF5307 bus in order to establish interface requirements.

  • Page 523

    Epson Research and Development Page 9 Vancouver Design Center The following figure illustrates a typical memory read cycle on the MCF5307 system bus. BCLK0 A[31:0] SIZ[1:0], TT[1:0] D[31:0] Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete...

  • Page 524

    They are typically not used for transfers to/from IO peripheral devices such as the S1D13504. The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them.

  • Page 525

    MCF5307’s General-Purpose Chip Select Module. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 526

    CPU is reading data from the S1D13504. • WAIT# is a signal which is output from the S1D13504 to the host CPU which indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host...

  • Page 527

    The interface between the S1D13504 and the MCF5307 requires minimal glue logic. Since the S1D13504 has a single chip select input for both display RAM and registers, a single external gate is required to produce a negative-OR function of the two MCF5307 chip selects.

  • Page 528

    Vancouver Design Center 4.2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

  • Page 529

    2M byte block size. 4.4 MCF5307 Chip Select Configuration In the example interface, chip selects 4 and 5 are used to control the S1D13504. CS4 selects a 2M byte address space for the S1D13504 control registers, while CS5 selects the 2M byte display buffer.

  • Page 530

    Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 531

    • Epson Research and Development, Inc., S1D13504 Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S1U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.

  • Page 532

    Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan, R.O.C. Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway &...

  • Page 533

    The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

  • Page 534

    Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A-G-012-05 Issue Date: 01/10/26...

  • Page 535

    ....... . 8 S1D13504 Host Bus Interface ......9 Generic MPU Host Bus Interface Pin Mapping .

  • Page 536

    Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A-G-012-05 Issue Date: 01/10/26...

  • Page 537

    Table 5-2: TX3912 to PC Card Slots Address Remapping using the IT8368E ... . 19 Table 5-3: S1D13504 Configuration using the IT8368E ..... . . 20 Table 5-4: S1D13504 Host Bus Selection using the IT8368E.

  • Page 538

    Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A-G-012-05 Issue Date: 01/10/26...

  • Page 539

    1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Toshiba TX3912 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.

  • Page 540

    2 Interfacing to the TX3912 The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13504 connects to the TX3912 processor. The S1D13504 can be successfully interfaced using one of three configurations: •...

  • Page 541

    S1D13504 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

  • Page 542

    3.2 Generic MPU Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

  • Page 543

    Oscillator CLKI Note: When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of TX3912 to S1D13504 Direct Connection Note For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.

  • Page 544

    Section 5, “System Design Using the IT8368E PC Card Buffer” on page 14). All other addresses are ignored. The S1D13504 address ranges, as seen by the TX3912 on the PC Card slot 1 memory space, are as follows: • 6400 0000h: S1D13504 registers aliased 131,072 times at 64 byte intervals over 8M bytes.

  • Page 545

    Vancouver Design Center 4.3 S1D13504 Hardware Configuration The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

  • Page 546

    S1D13504 can be interfaced with the TX3912 without using a PC Card slot. Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot.

  • Page 547

    Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that amy reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

  • Page 548

    Vancouver Design Center The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether...

  • Page 549

    Logic Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the S1D13504 Hardware Functional Specification , document number X19A-A-002-xx). When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that amy reset the S1D13504 (e.g.

  • Page 550

    When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13504. When accessing the S1D13504 the associated card-side signals are disabled in order to avoid any conflicts.

  • Page 551

    CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the TX3912 is divided into Attribute, IO and S1D13504 access. Table 5-2:, “TX3912 to PC Card Slots Address Remapping using the IT8368E” provides all the details of the Attribute/IO address re-allocation by the IT8368E.

  • Page 552

    Vancouver Design Center 5.5 S1D13504 Configuration The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

  • Page 553

    Vancouver Design Center 6 Software Test utilities and display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source.

  • Page 554

    • Epson Research and Development, Inc., S1D13504 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. • Epson Research and Development, Inc., S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. • Epson Research and Development, Inc., S1D13504 Programming Notes and Examples, Document Number X19A-G-002-xx.

  • Page 555

    Epson Research and Development Page 23 Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13504) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.

  • Page 556

    Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A-G-012-05 Issue Date: 01/10/26...

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