Direct Connection To The Toshiba Tx3912; Hardware Description - Epson S1D13506 Technical Manual

Epson Research and Development
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4 Direct Connection to the Toshiba TX3912

4.1 Hardware Description

ENDIAN
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
The S1D13506 was specifically designed to support the Toshiba MIPS TX3912 processor.
When configured, the S1D13506 will utilize one of the PC Card slots supported by the
processor.
In this example implementation, the S1D13506 occupies one PC Card slot and resides in
the Attribute and IO address range. The processor provides address bits A[12:0], with
A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring
more than 8K bytes of address space would require an external latch for these multiplexed
bits. However, the S1D13506 has an internal latch specifically designed for this processor
making additional logic unnecessary. To further reduce the need for external components,
the S1D13506 has an optional BUSCLK divide-by-2 feature, allowing the high speed
DCLKOUT from the processor to be directly connected to the BUSCLK input of the
S1D13506. An optional external oscillator may be used for BUSCLK since the S1D13506
will accept host bus control signals asynchronously with respect to BUSCLK.
The following diagram shows a typical implementation of the interface.
TX3912
A[12:0]
D[23:16]
D[31:24]
ALE
CARDREG*
CARDIORD*
CARDIOWR*
CARDxCSH*
CARDxCSL*
RD*
WE*
V
DD
CARDxWAIT*
DCLKOUT ...or...
Figure 4-1: Typical Implementation of Direct Connection
V (+3.3V)
DD
S1D13506
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
AB20
AB19
AB18
AB17
WE1#
RD/WR#
RD#
WE0#
pull-up
WAIT#
System RESET
RESET#
Oscillator BUSCLK
CLKI
See text
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