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S1D13504
Epson S1D13504 Manuals
Manuals and User Guides for Epson S1D13504. We have
2
Epson S1D13504 manuals available for free PDF download: Technical Manual
Epson S1D13504 Technical Manual (556 pages)
Color Graphics LCD/CRT Controller
Brand:
Epson
| Category:
Controller
| Size: 5 MB
Table of Contents
This Page Left Blank
9
Table of Contents
9
1 Introduction
17
Scope
17
Overview Description
17
2 Features
18
Memory Interface
18
CPU Interface
18
Display Support
18
Display Modes
19
Clock Source
19
Miscellaneous
19
Package and Pin
19
Table 2-1: S1D13504 Series Package List
19
3 Typical System Implementation Diagrams
20
Figure 3-1: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
20
Figure 3-2: Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
20
Figure 3-3: Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
21
Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
21
4 Block Description
22
Functional Block Diagram
22
Figure 4-1: System Block Diagram Showing Datapaths
22
Functional Block Descriptions
23
Display FIFO
23
Host Interface
23
LCD Interface
23
Look-Up Table
23
Memory Controller
23
Power Save
23
5 Pin out
24
Pinout Diagram for S1D13504F00A
24
Figure 5-1: Pinout Diagram of F00A
24
Pinout Diagram for S1D13504F01A
25
Figure 5-2: Pinout Diagram of F01A
25
Pinout Diagram for S1D13504F02A
26
Figure 5-3: Pinout Diagram of F02A
26
Pin Description
27
Host Interface
27
Table 5-1: Host Interface Pin Descriptions
27
Memory Interface
30
Table 5-2: Memory Interface Pin Descriptions
30
Clock Input
32
LCD Interface
32
Table 5-3: LCD Interface Pin Descriptions
32
Table 5-4: Clock Input Pin Description
32
CRT and External RAMDAC Interface
33
Table 5-5: CRT and RAMDAC Interface Pin Descriptions
33
Miscellaneous
35
Power Supply
35
Table 5-6: Miscellaneous Pin Descriptions
35
Table 5-7: Power Supply Pin Descriptions
35
Summary of Configuration Options
36
Table 5-8: Summary of Power on / Reset Options
36
Multiple Function Pin Mapping
37
Table 5-9: Host Bus Interface Pin Mapping
37
Table 5-10: Memory Interface Pin Mapping
38
Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping
39
6 C. Characteristics
40
Table 6-1: Absolute Maximum Ratings
40
Table 6-2: Recommended Operating Conditions
40
Table 6-3: Input Specifications
40
Table 6-4: Output Specifications
41
7 C. Characteristics
42
CPU Interface Timing
42
Figure 7-1: SH-3 Interface Timing
42
Interface Timing
42
Table 7-1: SH-3 Interface Timing
43
MC68K Bus 1 Interface Timing (E.g. MC68000)
44
Figure 7-2: MC68K Bus 1 Interface Timing
44
Table 7-2: MC68K Bus 1 Interface Timing
45
MC68K Bus 2 Interface Timing (E.g. MC68030)
46
Figure 7-3: MC68K Bus 2 Interface Timing
46
Table 7-3: MC68K Bus 2 Interface Timing
47
Generic MPU Interface Synchronous Timing
48
Figure 7-4: Generic MPU Interface Synchronous Timing
48
Table 7-4: Generic MPU Interface Synchronous Timing
49
Generic MPU Interface Asynchronous Timing
50
Figure 7-5: Generic MPU Interface Asynchronous Timing
50
Table 7-5: Generic MPU Interface Asynchronous Timing
51
Clock Input Requirements
52
Memory Interface Timing
52
EDO-DRAM Read Timing
52
Figure 7-6: Clock Input Requirements
52
Figure 7-7: EDO-DRAM Read Timing
52
Table 7-6: Clock Input Requirements
52
Table 7-7: EDO DRAM Read Timing
53
EDO-DRAM Write Timing
54
Figure 7-8: EDO-DRAM Write Timing
54
Table 7-8: EDO DRAM Write Timing
55
EDO-DRAM Read-Write Timing
56
Figure 7-9: EDO-DRAM Read-Write Timing
56
Table 7-9: EDO DRAM Read-Write Timing
57
EDO-DRAM cas before RAS Refresh Timing
58
Figure 7-10: EDO-DRAM cas before RAS Refresh Timing
58
Table 7-10: EDO-DRAM cas before RAS Refresh Timing
58
EDO-DRAM Self-Refresh Timing
59
Figure 7-11: EDO-DRAM Self-Refresh Timing
59
Table 7-11: EDO-DRAM Self-Refresh Timing
59
Figure 7-12: FPM-DRAM Read Timing
60
FPM-DRAM Read Timing
60
Table 7-12: FPM DRAM Read Timing
61
Figure 7-13: FPM-DRAM Write Timing
62
FPM-DRAM Write Timing
62
Table 7-13: FPM-DRAM Write Timing
63
Figure 7-14: FPM-DRAM Read-Write Timing
64
FPM-DRAM Read-Write Timing
64
Table 7-14: FPM-DRAM Read-Write Timing
65
Figure 7-15: FPM-DRAM CAS# before RAS# Refresh Timing
66
FPM-DRAM CAS# before RAS# Refresh Timing
66
Table 7-15: FPM-DRAM CAS# before RAS# Refresh Timing
66
Figure 7-16: FPM-DRAM CBR Self-Refresh Timing
67
FPM-DRAM Self-Refresh Timing
67
Table 7-16: FPM-DRAM CBR Self-Refresh Timing
67
Display Interface
68
Figure 7-17: LCD Panel Power-On/Reset Timing
68
Power-On/Reset Timing
68
Table 7-17: LCD Panel Power-On/Reset Timing
68
Figure 7-18: LCD Panel Suspend Timing
69
Suspend Timing
69
Table 7-18: LCD Panel Suspend Timing
69
Figure 7-19: Single Monochrome 4-Bit Panel Timing
70
Single Monochrome 4-Bit Panel Timing
70
Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing
71
Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing
71
Figure 7-21: Single Monochrome 8-Bit Panel Timing
72
Single Monochrome 8-Bit Panel Timing
72
Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing
73
Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing
73
Figure 7-23: Single Color 4-Bit Panel Timing
74
Single Color 4-Bit Panel Timing
74
Figure 7-24: Single Color 4-Bit Panel A.C. Timing
75
Table 7-21: Single Color 4-Bit Panel A.C. Timing
75
Figure 7-25: Single Color 8-Bit Panel Timing (Format 1)
76
Single Color 8-Bit Panel Timing (Format 1)
76
Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)
77
Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
77
Figure 7-27: Single Color 8-Bit Panel Timing (Format 2)
78
Single Color 8-Bit Panel Timing (Format 2)
78
Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2)
79
Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2)
79
Figure 7-29: Single Color 16-Bit Panel Timing
80
Single Color 16-Bit Panel Timing
80
Figure 7-30: Single Color 16-Bit Panel A.C. Timing
81
Table 7-24: Single Color 16-Bit Panel A.C. Timing
81
Dual Monochrome 8-Bit Panel Timing
82
Figure 7-31: Dual Monochrome 8-Bit Panel Timing
82
Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing
83
Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing
83
Dual Color 8-Bit Panel Timing
84
Figure 7-33: Dual Color 8-Bit Panel Timing
84
Figure 7-34: Dual Color 8-Bit Panel A.C. Timing
85
Table 7-26: Dual Color 8-Bit Panel A.C. Timing
85
Dual Color 16-Bit Panel Timing
86
Figure 7-35: Dual Color 16-Bit Panel Timing
86
Figure 7-36: Dual Color 16-Bit Panel A.C. Timing
87
Table 7-27: Dual Color 16-Bit Panel A.C. Timing
87
16-Bit TFT Panel Timing
88
Figure 7-37: 16-Bit TFT Panel Timing
88
Figure 7-38: TFT A.C. Timing
89
Table 7-28: TFT A.C. Timing
90
CRT Timing
91
Figure 7-39: CRT Timing
91
Figure 7-40: CRT A.C. Timing
92
Table 7-29: CRT A.C. Timing
93
External RAMDAC Read / Write Timing
94
Figure 7-41: Generic Bus RAMDAC Read / Write Timing
94
Table 7-30: Generic Bus RAMDAC Read / Write Timing
94
8 Registers
95
Register Mapping
95
Register Descriptions
95
Revision Code Register
95
Table 8-1: S1D13504 Addressing
95
Memory Configuration Registers
96
Table 8-2: DRAM Refresh Rate Selection
96
Panel/Monitor Configuration Registers
97
Table 8-3: Panel Data Width Selection
97
Table 8-4: FPLINE Polarity Selection
99
Table 8-5: FPFRAME Polarity Selection
101
Display Configuration Registers
102
Table 8-6: Simultaneous Display Option Selection
102
Table 8-7: Number of Bits-Per-Pixel Selection
103
Table 8-8: Pixel Panning Selection
106
Clock Configuration Register
107
Power Save Configuration Registers
107
Table 8-10: Suspend Refresh Selection
107
Table 8-9: PCLK Divide Selection
107
Miscellaneous Registers
108
Table 8-11: Minimum Memory Timing Selection
113
Table 8-12: RAS-To-CAS Delay Timing Select
114
Table 8-13: RAS Precharge Timing Select
114
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency
115
Look-Up Table Registers
116
Table 8-15: RGB Index Selection
116
External RAMDAC Control Registers
117
9 Display Buffer
119
Table 9-1: S1D13504 Addressing
119
Figure 9-1: Display Buffer Addressing
119
Half Frame Buffer
120
Image Buffer
120
10 Display Configuration
121
Display Mode Data Format
121
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
121
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
122
Image Manipulation
123
Figure 10-3: Image Manipulation
123
11 Clocking
124
Maximum MCLK: PCLK Ratios
124
Table 11-1: Maximum PCLK Frequency with EDO-DRAM
124
Table 11-2: Maximum PCLK Frequency with FPM-DRAM
124
Frame Rate Calculation
125
Table 11-3: Example Frame Rates
125
12 Look-Up Table Architecture
127
Gray Shade Display Modes
127
Table 12-1: Look-Up Table Configurations
127
Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture
127
Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture
128
Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture
128
Color Display Modes
129
Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture
129
Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture
130
Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture
131
Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture
132
13 Power Save Modes
133
Hardware Suspend
133
Software Suspend
133
Power Save Mode Function Summary
134
Pin States in Power Save Modes
134
Table 13-1: Power Save Mode Function Summary
134
Table 13-2: Pin States in Power Save Modes
134
14 Mechanical Data
135
Qfp15-128 (S1D13504F00A)
135
Figure 14-1: Mechanical Drawing QFP15-128
135
Tqfp15-128 (S1D13504F01A)
136
Figure 14-2: Mechanical Drawing TQFP15-128
136
Qfp20-144 (S1D13504F02A)
137
Figure 14-3: Mechanical Drawing QFP20-144
137
15 References
138
16 Sales and Technical Support
139
This Page Left Blank
143
1 Introduction
147
2 Programming the S1D13504 Registers
148
Registers Requiring Special Consideration
148
REG[01] Bit 0 - Memory Type
148
REG[02] Bit 1 - Dual/Single Panel Type
148
REG[22] Bits 7-2 - Performance Enhancement Register 0
148
REG[1B] Bit 0 - Half Frame Buffer Disable
149
REG[23] Display FIFO
149
Register Initialization
149
Initialization Sequence
149
Initialization Example
150
Re-Programming Registers
151
Disabling the Half Frame Buffer Sequence
151
3 Display Buffer
152
Display Buffer Location
152
Display Buffer Organization
152
Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
152
Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
152
Memory Organization for Eight Bit-Per-Pixel (256 Colors)
153
Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
153
Memory Organization for 15 Bit-Per-Pixel (32768 Colors)
154
Memory Organization for 16 Bit-Per-Pixel (65536 Colors)
154
Look-Up Table (LUT)
155
Look-Up Table Registers
155
Look-Up Table Organization
157
4 Advanced Techniques
163
Virtual Display
163
Examples
164
Registers
164
Panning and Scrolling
165
Registers
166
Examples
167
Split Screen
168
Registers
168
Examples
169
5 LCD Power Sequencing and Power Save Modes
170
Introduction to LCD Power Sequencing
170
Introduction to Power Save Modes
170
Registers
170
Suspend Sequencing
171
Suspend Enable Sequence
171
Suspend Disable Sequence
172
LCD Enable/Disable Sequencing (Reg[0D] Bit 0)
172
6 CRT Considerations
173
Introduction
173
CRT Only
173
Simultaneous Display
174
7 Identifying the S1D13504
178
8 Hardware Abstraction Layer (HAL)
179
Introduction
179
Screen Manipulation
181
Color Manipulation
187
Drawing
190
Register Manipulation
192
Miscellaneous
192
9 Sample Code
194
Introduction
194
Sample Code Using 13504HAL API
194
Sample Code Without Using 13504HAL API
195
Appendix A Supported Panel Values
201
This Page Left Blank
208
13504Cfg.exe
212
Program Requirements
213
Installation
213
Usage
213
Script Mode
214
Interactive Mode
215
13504CFG Menu Bar
215
Viewing 13504CFG Menu Contents
215
Making 13504CFG Menu Selections
216
Files Menu
217
View Menu
218
Device Menu
220
Panel
221
Crt
223
Advanced Memory
225
Power Management
227
Lookup Table (LUT)
229
Setup
231
Help Menu
232
Comments
233
Sample Program Messages
233
13504Dcfg Menus
269
13504Dcfg
271
Installation
272
Usage
272
13504DCFG Configuration Tabs
273
General Tab
273
Preferences Tab
275
Memory Tab
276
Clocks Tab
279
Panel Tab
281
CRT Tab
285
Registers Tab
286
13504DCFG Menus
287
Export
287
Enable Tooltips
288
ERD on the Web
288
Update Common Controls
288
About 13504DCFG
288
Comments
289
This Page Left Blank
353
1 Introduction
357
Features
357
2 Installation and Configuration
358
3 LCD / RAMDAC Interface Pin Mapping
359
4 CPU / BUS Interface Connector Pinouts
360
5 Host Bus Interface Pin Mapping
362
6 Technical Description
363
ISA Bus Support
363
Non-ISA Bus Support
364
DRAM Support
364
Decode Logic
364
Clock Input Support
364
Monochrome LCD Panel Support
365
Color Passive LCD Panel Support
365
Color TFT LCD Panel Support
365
External CMOS RAMDAC Support
365
Power Save Modes
366
Core VDD Power Supply
366
IO VDD Power Supply
366
Adjustable LCD Panel Negative Power Supply
366
Adjustable LCD Panel Positive Power Supply
366
Cpu/Bus Interface Header Strips
367
Schematic Notes
367
7 Parts List
368
8 Schematic Diagrams
370
Table of Contents
379
2 Features
384
3 Installation and Configuration
385
Configuration Jumpers
386
4 Technical Description
390
PCI Bus Support
390
Non-PCI Host Interface Support
390
CPU Interface Pin Mapping
391
CPU Bus Connector Pin Mapping
392
LCD Support
394
LCD Interface Pin Mapping
395
Adjustable LCD Panel Positive Power Supply (VDDH)
396
Buffered LCD Connector
396
Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
396
Current Consumption Measurement
397
6 Parts List
399
7 Schematics
401
8 Board Layout
406
9 Technical Support
407
EPSON LCD/CRT Controllers (S1D13504)
407
Table of Contents
411
1 Introduction
415
2 Interfacing to the PR31500/PR31700
416
3 S1D13504 Host Bus Interface
417
Generic MPU Host Bus Interface Pin Mapping
417
Generic MPU Host Bus Interface Signals
418
4 Direct Connection to the Philips PR31500/PR31700
419
Hardware Description
419
Memory Mapping and Aliasing
420
S1D13504 Configuration
421
5 System Design Using the IT8368E PC Card Buffer
422
Hardware Description-Using One IT8368E
422
IT8368E Configuration
426
Memory Mapping and Aliasing
427
S1D13504 Configuration
428
6 Software
429
Table of Contents
439
1 Introduction
443
2 Interfacing to the NEC VR4102
444
The NEC VR4102 System Bus
444
Overview
444
LCD Memory Access Cycles
445
3 S1D13504 Host Bus Interface
446
Generic MPU Host Bus Interface Pin Mapping
446
Generic MPU Host Bus Interface Signals
447
4 VR4102 to S1D13504 Interface
448
Hardware Description
448
S1D13504 Hardware Configuration
449
5 Software
451
6 References
452
Documents
452
Document Sources
452
7 Technical Support
453
EPSON LCD/CRT Controllers (S1D13504)
453
NEC Electronics Inc. (VR4102)
453
This Page Left Blank
457
1 Introduction
461
2 Interfacing to the MC68328
462
The 68328 System Bus
462
Chip-Select Module
462
3 S1D13504 Host Bus Interface
463
Generic MPU Host Bus Interface Pin Mapping
463
Generic MPU Host Bus Interface Signals
464
4 MC68328 to S1D13504 Interface
465
Hardware Description
465
S1D13504 Hardware Configuration
467
MC68328 Chip Select Configuration
468
5 Software
469
6 References
470
Documents
470
Document Sources
470
7 Technical Support
471
EPSON LCD/CRT Controllers (S1D13504)
471
Motorola MC68328 Processor
471
Table of Contents
475
1 Introduction
479
2 Interfacing to the PC Card Bus
480
The PC Card System Bus
480
Memory Access Cycles
480
PC Card Overview
480
3 S1D13504 Host Bus Interface
482
Generic MPU Host Bus Interface Pin Mapping
482
Generic MPU Host Bus Interface Signals
483
4 PC Card to S1D13504 Interface
484
Hardware Description
484
S1D13504 Hardware Configuration
485
PAL Equations
486
Register/Memory Mapping
486
5 Software
487
6 References
488
Documents
488
Document Sources
488
7 Technical Support
489
EPSON LCD/CRT Controllers (S1D13504)
489
PC Card Standard
489
Table of Contents
493
1 Introduction
497
2 Interfacing to the MPC821
498
The Mpc8Xx System Bus
498
MPC821 Bus Overview
498
Normal (Non-Burst) Bus Transactions
499
Memory Controller Module
501
General-Purpose Chip Select Module (GPCM)
501
User-Programmable Machine (UPM)
502
3 S1D13504 Host Bus Interface
503
Generic MPU Host Bus Interface Pin Mapping
503
Generic MPU Host Bus Interface Signals
504
4 MPC821 to S1D13504 Interface
505
Hardware Description
505
Hardware Connections
506
S1D13504 Hardware Configuration
508
Register/Memory Mapping
509
MPC821 Chip Select Configuration
509
Test Software
510
Source Code
510
5 Software
512
6 References
513
Documents
513
Document Sources
513
7 Technical Support
514
EPSON LCD/CRT Controllers (S1D13504)
514
Motorola MPC821 Processor
514
Table of Contents
517
1 Introduction
521
2 Interfacing to the MCF5307
522
The MCF5307 System Bus
522
Normal (Non-Burst) Bus Transactions
522
Overview
522
Burst Cycles
524
Chip-Select Module
524
3 S1D13504 Bus Interface
525
Generic MPU Host Bus Interface Pin Mapping
525
Generic MPU Host Bus Interface Signals
526
4 MCF5307 to S1D13504 Interface
527
Hardware Connections
527
S1D13504 Hardware Configuration
528
Memory/Register Mapping
529
MCF5307 Chip Select Configuration
529
5 Software
530
6 References
531
Documents
531
Document Sources
531
7 Technical Support
532
EPSON LCD/CRT Controllers (S1D13504)
532
Motorola MCF5307 Processor
532
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Epson S1D13504 Technical Manual (274 pages)
Dot Matrix Graphics LCD Controller
Brand:
Epson
| Category:
Video Card
| Size: 1 MB
Table of Contents
Evaluation Board
3
Hardware Functional Specification
4
Programming Notes and Examples
4
Application Notes
4
Table of Contents
6
Introduction
12
Scope
12
Overview Description
12
Features
13
Memory Interface
13
CPU Interface
13
Display Support
13
Display Modes
14
Clock Source
14
Miscellaneous
14
Package and Pin
14
Table 2-1 S1D13504 Series Package List
14
Typical System Implementation Diagrams
15
Figure 3-1 Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
15
Figure 3-2 Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
15
Figure 3-3 Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
16
Figure 3-4 Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
16
Block Description
17
Functional Block Diagram
17
Functional Block Descriptions
17
Host Interface
17
Memory Controller
17
Display FIFO
17
Look-Up Table
17
LCD Interface
17
Power Save
17
Figure 4-1 System Block Diagram Showing Datapaths
17
Pin out
18
Pinout Diagram for S1D13504F00A
18
Figure 5-1 Pinout Diagram of S1D13504F00A
18
Pinout Diagram for S1D13504F01A
19
Figure 5-2 Pinout Diagram of S1D13504F01A
19
Pinout Diagram for S1D13504F02A
20
Figure 5-3 Pinout Diagram of S1D13504F02A
20
Pin Description
21
Host Interface
21
Table 5-1 Host Interface Pin Descriptions
21
Memory Interface
23
Table 5-2 Memory Interface Pin Descriptions
23
LCD Interface
24
Clock Input
24
CRT and External RAMDAC Interface
24
Table 5-3 LCD Interface Pin Descriptions
24
Table 5-4 Clock Input Pin Description
24
Table 5-5 CRT and RAMDAC Interface Pin Descriptions
24
Miscellaneous
25
Table 5-6 Miscellaneous Pin Descriptions
25
Power Supply
26
Table 5-7 Power Supply Pin Descriptions
26
Summary of Configuration Options
27
Multiple Function Pin Mapping
27
Table 5-8 Summary of Power on / Reset Options
27
Table 5-9 Host Bus Interface Pin Mapping
27
Table 5-10 Memory Interface Pin Mapping
27
Table 5-11 LCD, CRT, RAMDAC Interface Pin Mapping
28
C. Characteristics
29
Table 6-1 Absolute Maximum Ratings
29
Table 6-2 Recommended Operating Conditions
29
C. Characteristics
30
CPU Interface Timing
31
Interface Timing
31
Figure 7-1 SH-3 Interface Timing
31
Table 7-1 SH-3 Interface Timing
31
Figure 7-2 SH-3 Write Bus Timing
32
Table 7-2 SH-3 Write Bus Timing
32
MC68K Bus 1 Interface Timing (E.g. MC68000)
33
Figure 7-3 MC68000 Bus 1 Interfacetiming
33
Table 7-3 MC68000 Bus 1 Interfacetiming
33
Figure 7-4 MC68000 Read Bus Timing
34
Table 7-4 MC68000 Read Bus Timing
34
MC68K Bus 2 Interface Timing (E.g. MC68030)
35
Figure 7-5 MC68030 Bus 2 Interface Timing
35
Table 7-5 MC68030 Bus 2 Interface Timing
35
Figure 7-6 MC68030 Read Bus Timing
36
Table 7-6 MC68030 Read Bus Timing
36
Generic MPU Interface Synchronous Timing
37
Figure 7-7 Generic MPU Interface Synchronous Timing
37
Table 7-7 Generic MPU Interface Synchronous Timing
37
Figure 7-8 Generic Write Bus Synchronous Timing
38
Table 7-8 Generic Write Bus Synchronous Timing
38
Generic MPU Interface Asynchronous Timing
39
Figure 7-9 Generic MPU Interface Asynchronous Timing
39
Table 7-9 Generic MPU Interface Asynchronous Timing
39
Figure 7-10 Generic Write Bus Asynchronous Timing
40
Table 7-10 Generic Write Bus Asynchronoud Timing
40
Clock Input Requirements
41
Figure 7-11 Clock Input Requirements
41
Table 7-11 Clock Input Requirements
41
Memory Interface Timing
42
EDO-DRAM Read Timing
42
Figure 7-12 EDO-DRAM Read Timing
42
Table 7-12 EDO DRAM Read Timing
42
EDO-DRAM Write Timing
43
Figure 7-13 EDO-DRAM Write Timing
43
Table 7-13 EDO DRAM Write Timing
43
EDO-DRAM Read-Write Timing
44
Figure 7-14 EDO-DRAM Read-Write Timing
44
EDO-DRAM cas before RAS Refresh Timing
45
EDO-DRAM Self-Refresh Timing
45
Figure 7-15 EDO-DRAM cas before RAS Refresh Timing
45
Figure 7-16 EDO-DRAM Self-Refresh Timing
45
FPM-DRAM Read Timing
46
Figure 7-17 FPM-DRAM Read Timing
46
FPM-DRAM Write Timing
47
Figure 7-18 FPM-DRAM Write Timing
47
FPM-DRAM Read-Write Timing
48
Figure 7-19 FPM-DRAM Read-Write Timing
48
FPM-DRAM CAS# before RAS# Refresh Timing
49
FPM-DRAM Self-Refresh Timing
49
Figure 7-20 FPM-DRAM CAS# before RAS# Refresh Timing
49
Figure 7-21 FPM-DRAM CBR Self-Refresh Timing
49
Display Interface
50
Power on / Reset Timing
50
Figure 7-22 LCD Panel Power on / Reset Timing
50
Suspend Timing
51
Figure 7-23 LCD Panel Suspend Timing
51
Single Monochrome 4-Bit Panel Timing
52
Figure 7-24 Single Monochrome 4-Bit Panel Timing
52
Figure 7-25 Single Monochrome 4-Bit Panel A.C. Timing
53
Single Monochrome 8-Bit Panel Timing
54
Figure 7-26 Single Monochrome 8-Bit Panel Timing
54
Figure 7-27 Single Monochrome 8-Bit Panel A.C. Timing
55
Single Color 4-Bit Panel Timing
56
Figure 7-28 Single Color 4-Bit Panel Timing
56
Figure 7-29 Single Color 4-Bit Panel A.C. Timing
57
Single Color 8-Bit Panel Timing (Format 1)
58
Figure 7-30 Single Color 8-Bit Panel Timing (Format 1)
58
Figure 7-31 Single Color 8-Bit Panel A.C. Timing (Format 1)
59
Single Color 8-Bit Panel Timing (Format 2)
60
Figure 7-32 Single Color 8-Bit Panel Timing (Format 2)
60
Figure 7-33 Single Color 8-Bit Panel A.C. Timing (Format 2)
61
Single Color 16-Bit Panel Timing
62
Figure 7-34 Single Color 16-Bit Panel Timing
62
Figure 7-35 Single Color 16-Bit Panel A.C. Timing
63
Dual Monochrome 8-Bit Panel Timing
64
Figure 7-36 Dual Monochrome 8-Bit Panel Timing
64
Figure 7-37 Dual Monochrome 8-Bit Panel A.C. Timing
65
Dual Color 8-Bit Panel Timing
66
Figure 7-38 Dual Color 8-Bit Panel Timing
66
Figure 7-39 Dual Color 8-Bit Panel A.C. Timing
67
Dual Color 16-Bit Panel Timing
68
Figure 7-40 Dual Color 16-Bit Panel Timing
68
16-Bit TFT Panel Timing
70
CRT Timing
72
External RAMDAC Read / Write Timing
74
Registers
75
Register Mapping
75
Register Descriptions
76
Revision Code Register
76
Memory Configuration Registers
76
Panel/Monitor Configuration Registers
77
Display Configuration Registers
81
Clock Configuration Register
85
Power Save Configuration Registers
86
Miscellaneous Registers
87
Look-Up Table Registers
94
External RAMDAC Control Registers
96
Display Buffer
97
Image Buffer
98
Half Frame Buffer
98
Display Configuration
99
Display Mode Data Format
99
Image Manipulation
101
Clocking
102
Maximum MCLK : PCLK Ratios
102
Frame Rate Calculation
103
Look -U P Table Architecture
105
Gray Shade Display Modes
105
Bit-Per-Pixel Mode
105
Bit-Per-Pixel Mode
106
Color Display Modes
106
Bit-Per-Pixel Color Mode
106
Bit-Per-Pixel Color Mode
109
Power Save Modes
110
Hardware Suspend
110
Software Suspend
110
Power Save Mode Function Summary
111
Pin States in Power Save Modes
111
Introduction
120
Programming the S1D13504 Registers
121
Registers Requiring Special Consideration
121
REG[01] Bit 0 - Memory Type
121
REG[22] Bits 7-2 - Performance Enhancement Register 0
121
REG[02] Bit 1 - Dual/Single Panel Type
121
REG[1B] Bit 0 - Half Frame Buffer Disable
121
REG[23] Display FIFO
121
Register Initialization
122
Initialization Sequence
122
Initialization Example
122
Re-Programming Registers
123
Disabling the Half Frame Buffer Sequence
124
Display Buffer Location
125
Display Buffer Organization
125
Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
125
Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
125
Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
125
Memory Organization for Eight Bit-Per-Pixel (256 Colors)
126
Memory Organization for 15 Bit-Per-Pixel (32768 Colors)
126
Look-Up Table (LUT)
127
Look-Up Table Registers
127
Look-Up Table Organization
128
Advanced Techniques
132
Virtual Display
132
Registers
132
Examples
133
Panning and Scrolling
134
Registers
135
Examples
136
Split Screen
137
Registers
137
Examples
138
Lcd Power Sequencing and Power Save Modes
139
Introduction to LCD Power Sequencing
139
Introduction to Power Save Modes
139
Registers
139
Suspend Sequencing
140
Suspend Enable Sequence
140
LCD Enable/Disable Sequencing (REG[0D] Bit 0)
141
Crt Considerations
142
Introduction
142
CRT Only
142
Simultaneous Display
143
Identifying the S1D13504
145
Hardware Abstraction Layer (Hal)
146
Introduction
146
API for 13504HAL
146
Initialization
146
Screen Manipulation
148
Color Manipulation
152
Drawing
154
Register Manipulation
156
Miscellaneous
156
Sample Code
157
Introduction
157
Sample Code Using 13504HAL API
157
Sample Code Without Using 13504HAL API
158
Appendix Supported Panel Values
162
13504Cfg.exe Configuration Program
168
Program Requirements
168
Installation
168
Usage
169
Script Mode
169
Interactive Mode
170
13504CFG Menu Bar
170
Files Menu
171
View Menu
172
Device Menu
173
Help Menu
179
Comments
180
Sample Program Messages
180
13504Show Demonstration Program
181
13504Show D P
181
S1D13504 Supported Evaluation Platforms
181
Installation
181
Usage
181
Comments
182
Program Messages
182
13504Splt Display Utility
183
S1D13504 Supported Evaluation Platforms
183
Installation
183
Usage
183
13504SPLT Example
184
Comments
184
Program Messages
184
13504Virt Display Utility
185
S1D13504 Supported Evaluation Platforms
185
Installation
185
Usage
185
13504VIRT Example
186
Comments
186
Program Messages
186
13504Play Diagnostic Utility
187
S1D13504 Supported Evaluation Platforms
187
Installation
187
Usage
187
13504PLAY Example
189
Scripting
189
Comments
189
Program Messages
192
Installation
193
Usage
193
Introduction
199
Features
199
Installation and Configuration
200
Cpu/Bus Interface Connector Pinouts
202
Host Bus Interface Pin Mapping
204
Technical Description
205
ISA Bus Support
205
Non-ISA Bus Support
205
DRAM Support
205
Decode Logic
206
Clock Input Support
206
Monochrome LCD Panel Support
206
Color Passive LCD Panel Support
206
Color TFT LCD Panel Support
206
External CMOS RAMDAC Support
206
Core V DD Power Supply
207
Power Save Modes
207
Power Supply
207
Adjustable LCD Panel Negative Power Supply
207
Adjustable LCD Panel Positive Power Supply
207
Cpu/Bus Interface Header Strips
207
Schematic Notes
207
Parts List
208
Schematic Diagrams
209
Interfacing to the Philips Mips Pr31500/Pr31700 Processor
219
Introduction
219
General Description
219
Direct Connection to the Philips PR31500/PR31700
220
Hardware Description
220
Memory Mapping and Aliasing
221
S1D13504 Configuration
221
System Design Using the IT8368E PC Card Buffer
222
Hardware Description-Using One IT8368E
222
IT8368E Configuration
224
S1D13504 Configuration
225
Software
226
Interfacing to the Nec V R 4102 Tm Microprocessor
227
Introduction
227
General Description
227
Rtm
227
Hardware Description
228
Software
229
Interfacing to the Pc Card Bus
230
Nterfacing to the Pc Card Us
230
Introduction
230
Interfacing to the PC Card Bus
231
The PC Card System Bus
231
S1D13504 Host Bus Interface
233
Bus Interface Modes
233
Generic MPU Host Bus Interface
234
PC Card to S1D13504 Interface
235
Hardware Description
235
S1D13504 Hardware Configuration
236
PAL Equations
236
Register/Memory Mapping
237
Software
238
References
239
Documents
239
Document Sources
239
Interfacing to the Motorola Mpc821 Microprocessor
240
Introduction
240
Interfacing to the MPC821
241
The Mpc8Xx System Bus
241
Overview
241
Memory Controller Module
244
User-Programmable Machine (UPM)
244
S1D13504 Bus Interface
245
Bus Interface Modes
245
Generic Bus Interface Mode
246
MPC821/S1D13504 Interface
247
Hardware Connections
247
S1D13504 Hardware Configuration
249
MPC821 Chip Select Configuration
250
Test Software
251
References
252
Documents
252
Document Sources
252
Interfacing to the Motorola Mmcf5307 Microprocessor
254
Interfacing to the MCF5307
254
The MCF5307 System Bus
254
Overview
254
Normal (Non-Burst) Bus Transactions
254
Chip-Select Module
255
S1D13504 Bus Interface
256
Bus Interface Modes
256
Generic Bus Interface Mode
257
MCF5307 to S1D13504 Interface
258
Hardware Connections
258
S1D13504 Hardware Configuration
259
MCF5307 Chip Select Configuration
260
References
261
Documents
261
Document Sources
261
Interfacing to the Toshiba Mips Tx3912 Processor
262
Introduction
262
General Description
262
Direct Connection to the Toshiba TX3912
263
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