Dual Color 16-Bit Panel Timing; Figure 7-41: Dual Color 16-Bit Panel Timing - Epson S1D13506 Technical Manual

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7.5.10 Dual Color 16-Bit Panel Timing

FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT[15,11]
FPDAT[14,10]
FPDAT[13,9]
FPDAT[12,8]
FPDAT[7,3]
FPDAT[6,2]
FPDAT[5,1]
FPDAT[4,0]
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
S1D13506
X25B-A-001-12
LINE 1/241 LINE 2/242 LINE 3/243
1-R1, 1-B3,
241-R1 2 41-B 3
1-G1, 1-R4,
24 1-G 1 2 41 -R 4
1-B1, 1-G 4,
2 41-B 1 2 41-G 4
1-R2, 1-B4,
2 41-R 2 2 41-B 4
1-G2, 1-R5,
24 1-G 2 2 41 -R 5
1-G 5,
1-B2,
2 41-G 5
2 41-B 2
1-R3, 1-B 5,
2 41-R 3
2 41-B 5
1-G3, 1-R6,
24 1-G 3 2 41 -R 6

Figure 7-41: Dual Color 16-Bit Panel Timing

= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
VDP
LINE 4/244 LINE 239/479 LINE 240/480
HDP
Epson Research and Development
Vancouver Design Center
VNDP
LINE 1/241 LINE 2/242
HNDP
1-G 63 8,
2 41-G 63 8
1-B 63 8,
241-B 638
1-R639 ,
241 -R639
1-G 63 9,
2 41-G 63 9
1-B 63 9,
2 41-B63 9
1-R640 ,
241 -R640
1-G 640,
2 41-G 64 0
1-B 64 0,
2 41-B64 0
Hardware Functional Specification
Issue Date: 02/03/26