Register/Memory Mapping - Epson S1D13506 Technical Manual

Epson Research and Development
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4.4 Register/Memory Mapping

Note
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
The S1D13506 is a memory mapped device. The SA-1110 will use the memory assigned
to a chip select (nCS4 in this example) to map the S1D13506 internal registers and display
buffer. The internal registers require 2M bytes of memory and are mapped to the lower
memory address space starting at zero. The display buffer also requires 2M bytes and is
mapped in the third and fourth megabytes (ranging from 200000h to 3FFFFFh).
This implementation decodes as shown in the following table.
Table 4-2: Register/Memory Mapping for Typical Implementation
M/R# (A21)
0
1 20 0000h - 3F FFFFh
Each chip select on the SA-1110 provides 64M bytes of address space. Without further
resolution of the decoding logic (M/R# connected to A21), the entire register set and
display buffer are aliased for every 4M byte boundary within the specified address range of
the chip select. Since address bits A[25:22] are ignored, the S1D13506 registers and display
buffer are aliased 16 times.
If aliasing is not desirable, the upper addresses must be fully decoded.
Address Range
0 - 1F FFFFh
Function
Internal Registers
Display Buffer
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S1D13506
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