Table 8-30: Bitblt Fifo Data Available - Epson S1D13506 Technical Manual

Page 162
bit 6
BitBLT FIFO Full
Status (REG[100h]
bit 5
bit 4
bit 1
bit 0
S1D13506
X25B-A-001-12
BitBLT FIFO Not-Empty Status
This is a read-only status bit.
When this bit = 1, the BitBLT FiFO has at least one data.
When this bit = 0, the BitBLT FIFO is empty.
To reduce system memory read latency, software can monitor this bit prior to a BitBLT
read burst operation.
The following table shows the number of data available in BitBLT FIFO under different
status conditions.

Table 8-30: BitBLT FIFO Data Available

BitBLT FIFO Half
Full Status
Bit 4) (REG[100h] Bit 5)
0 0
0 0
0 1
1 1
BitBLT FIFO Half Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBLT write burst operations.
When this bit = 1, the BitBLT FIFO is half full or greater than half full.
When this bit = 0, the BitBLT FIFO is less than half full.
BitBLT FIFO Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBLT write burst operations.
When this bit = 1, the BitBLT FIFO is full.
When this bit = 0, the BitBLT FIFO is not full.
BitBLT Destination Linear Select
When this bit = 1, the Destination BitBLT is stored as a contiguous linear block of mem-
ory.
When this bit = 0, the Destination BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
BitBLT Source Linear Select
When this bit = 1, the Source BitBLT is stored as a contiguous linear block of memory.
When this bit = 0, the Source BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
BitBLT FIFO Not Number of Data
Empty Status available in BitBLT
(REG[100h] Bit 6)
0
1
1
1 15 to 16
Epson Research and Development
Vancouver Design Center
FIFO
0
1 to 6
7 to 14
Hardware Functional Specification
Issue Date: 02/03/26