Table 7-3: Hitachi Sh-3 Timing - Epson S1D13506 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Clock frequency
CKIO
T Clock period
CKIO
t2 Clock pulse width low
t3 Clock pulse width high
t4 A[20:1], M/R#, RD/WR# setup to CKIO
t5 A[20:1], M/R#, RD/WR# hold from CSn#
t6 BS# setup
t7 BS# hold
t8 CSn# setup
t9 Falling edge RD# to D[15:0] driven
t10 Rising edge CSn# to WAIT# tri-state
t11 Falling edge CSn# to WAIT# driven
t12 CKIO to WAIT# delay
t13 D[15:0] setup to 2
t14 D[15:0] hold (write cycle)
t15 D[15:0] valid to WAIT# rising edge (read cycle)
t16 Rising edge RD# to D[15:0] tri-state (read cycle)
t17 CSn# high setup to CKIO
1. Two software WAIT states are required when f
2. One software WAIT state is required when f
Hardware Functional Specification
Issue Date: 02/03/26

Table 7-3: Hitachi SH-3 Timing

Parameter
nd
CKIO after BS# (write cycle)
CKIO
is greater than 33MHz.
CKIO
3.0V
Min
1/f
CKIO
6
6
4
0
4
3
3
3
2
3
4
0
0
0
6
3
is greater than 33MHz.
1 2
5.0V
Max Min Max
66 66
1/f
CKIO
6
6
3
0
3
2
3
2
10 1 6
16 2 10
20 3 13
0
0
0
30 3 15
2
S1D13506
X25B-A-001-12
Page 53
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns